;===================================================================================
;file name:		ccu_mpc8280.cfg
;file description:	bdiGDB configuration file for ccu board
;version:		1.0
;time_data:		14:53 2006-5-6
;author:		WangFei
;update description:		
;reference docs:	MPC8280RM(Rev. 1, 12/2005),MPC8280EC(Rev. 1.5, 03/2006),
;			Manual Version 1.19 for BDI2000,MPC8280G2CORERM/D6/2003Rev.1
;=========================================START======================================
[INIT]
;opcode		reg.address		opdata		comment						
;------------------------------------------------------------------------------------
;WGPR		register		value		;write value to the selected general purpose reg.
;WSPR		register		value		;write value to the selected special purpose reg.
;WSR		register		value		;write value to the selected segment reg.
;WREG		name			value		;write value to the selected CPU reg. by name
;DELAY					value		;delay value ms(1~30000)
;WMn		address			value		;write a value to the selected memory place
							;n=8,16,32,64
;RMn		address			value		;read a value to the selected memory place
							;n=8,16,32,64
;SUPM		memaddr			mdraddr		;start a sequence of writes to the UPM RAM array(82xx)
;WUPM		dummy			data		;write to the UPM RAM array(*mdraddr=data,*memaddr=0)
;TSZ1		start			end		;defines a memory range with 1byte maximal transfer size
;TSZ2		start			end		;defines a memory range with 2byte maximal transfer size
;TSZ4		start			end		;defines a memory range with 4byte maximal transfer size
;MMAP		start			end		;define up to 32 valid memory ranges
;------------------------------------------------------------------------------------
;------------init core register-------------------
WREG		MSR			0x00000000	;MRS 清除MRS寄存器，禁用中斷
WM32		0x000101A8		0xf0000000	;IMMR 定義內部寄存器基址為0xf0000000
WM32		0xf0010004		0xffffff00	;SYPCR 禁用看門狗、禁用總線監視
WM32		0xf0010c80		0x00000001	;SCCR 波特率時鐘為主時鐘/16 
;WM32		0xf0010024		0x00908210	;BCR 單處理器模式，32位總線，不使用地址線做BANKSEL
WM32		0xf0010024		0x00800210	;BCR 單處理器模式，32位總線，使用地址線做BANKSEL                                                
WM32		0xf0010000		0x00240C00	;SIUMCR 使能內核，配置bctl1為nOE，使能BANKSEL腳                                                       
;WM32		0xf0010000		0x00040C00	;SIUMCR 使能內核，配置bctl1為nOE,不使能BANKSEL腳
delay		20					;delay 20ms
;-------------------------------------------------
;                           
;--------------------init flash-------------------
WM32		0xf0010104		0xFC000EF4	;OR0 Flash大小為64MB(兩片32MB@16位級聯)
WM32		0xf0010100		0xFC001801	;BR0 Flash基地址為0xFC000000, 32bit, no parity
delay		20					;delay 20ms
;-------------------------------------------------
;
;--------------------init 61580-------------------					
;WM32		0xf0010114		0xFF000EF6	;OR2 
;WM32		0xf0010110		0x40001001	;BR2 
;delay		20					;delay 20ms
;-------------------------------------------------
;
;---------init SDRAM Init (PPC bus)---------------
WM16		0xf0010184		0x0a00		;MPTPR Divide Bus clock by 41應該由SDRAM資料確定
WM8		0xf001019C		0x20		;PSRT Divide MPTPR output by 20由SDRAM資料確定
WM32		0xf0010190		0xc34a2163	;PSDMR 定義模式、段選地址等
WM32		0xf001010C		0xfc002d00	;OR1 64MB, 4 banks, row start at A6, 13 rows
WM32		0xf0010108		0x00001841	;BR1 SDRAM @0x00000000, 32bit, no parity
WM8		0xf0010190		0xeb		;PSDMR Precharge all banks SMMR[OP]=101
WM8		0x00000110		0xff            ;
delay					20		;delay 20ms
WM8		0xf0010190		0xcb		;Issue 8 CBR_Refresh commands  SMMR[OP]=001
WM8		0xf0010190		0xcb
WM8		0xf0010190		0xcb
WM8		0xf0010190		0xcb
WM8		0xf0010190		0xcb
WM8		0xf0010190		0xcb
WM8		0xf0010190		0xcb
WM8		0xf0010190		0xcb
WM8		0x00000110		0xff            ;
WM8		0xf0010190		0xdb		;Issue Mode set command  PSDMR[OP]=011
WM8		0x00000110		0xff            ;
WM8		0xf0010190		0xc3		;set PSDMR for normal operation
TSZ4		0x00000000		0x00002000      ;定義一個4byte存取的空間
delay		20					;delay 20ms
;-------------------------------------------------
;
;--------------------init user test IO------------
WM32		0xf0010d0c		0x00000000	;PA28為非三態輸出
WM32		0xf0010d04		0xFFFFFFF7	;PA28為IO管腳
WM32		0xf0010d00		0x00000008	;PA28為IO輸出管腳
WM32		0xf0010d10		0x00000000	;PA28為低電平，此時IO測試LED應該點亮
;****使用mm 0xf0010d10 0x00000007 命令應該能熄滅接的LED****                                                       
;-------------------------------------------------
;--------------------init timer1------------------
WM32		0xf0010d44		0xFFFFFFFF	;PC30為功能腳
WM32		0xf0010d48		0xFFFFFFFF	;PC30第二功能腳
WM32		0xf0010d40		0xFFFFFFFF	;PC30為功能輸出管腳
WM16		0xf0010d90		0xFF2C		;自動復位，timer_clk_in=bus_iner_clk/16/256
WM16		0xf0010d94		0x0004		;計數器閾值為4,timer_clk_out=timer_clk_in/閾值*2  
WM8		0xf0010d84		0x2A		;禁用定時器3、4 
WM8		0xf0010d80		0x29		;使能定時器1，禁用定時器2                                                   
;-------------------------------------------------
[TARGET]
;opcode		opdata			comment						
;------------------------------------------------------------------------------------
;CPUTYPE	type[32]		;select the type of CUP,[32] mean PPC core works in 32 bit data bus
;JTAGCLOCK	value			;lelect the JTAG clock rate the BDI2000 uses to communicate with CPU
;BDIMODE	mode[param]		;select the BDI debugging mode
;STARTUP	mode[runtime]		;select the target startup mode
;BOOTADDR	address			;BDI set a hardware breakpoint at this address auto
;WORKSPACE	address			;a ram space(256bytes at less) for faster downloadand flush the data cache
;BREAKMODE	mode			;define how breakpoints are implementd
;STEPMODE	mode			;defines how single step is implemented
;VECTOR		CATCH			;BDI catch all unhandled exceptions(while 0x00000000~0x00001fff is writable)
;DCACHE		mode			;define if the BDI flushes the data cache before it accesses memory
;POWERUP	delay			;delay in ms before BDI begin JTAG mommunication
;WAKEUP		time			;define a delay time(ms) the BDI inserts between releasing cop-hr and start
;MEMDELAY	clocks			;increase the number of clocks used to execute a memory access cycle
;L2PM		base	size		;define the base address and size of the L2 cache private memory
;MMU		XLAT[kb]		;in order to support Linux kernel debugging
;PTBASE		addr			;define the physical memory address when the BDI look for the virtual address
;PARITY		ON			;the BDI generates the data write parity bits
;REGLIST	list			;
;VIO		port[baudrate]		;use when the optional Rx/Tx pins of the COP connector are routed to a UART
;SIO		port[baudrate]		;use when a TCP/IP channel is routed to the BDI's RS232 connector
;SCANPRED	count	irlen		;give the BDI information about JTAG devices present before the PowerPC in
;SCANSUCC	count	irlen		;give the BDI information about JTAG devices present after the PowerPC in 	
;------------------------------------------------------------------------------------
;-------------------------------------------------
CPUTYPE		8280			;the CPU typeis mpc8280
JTAGCLOCK	3			;use 4.1MHz JTAG clock
BDIMODE		AGENT			;the BDI working mode is AGENT(LOADONLY | AGENT [RUN])
WORKSPACE	0x00000000		;use faster download mode&flush the data cache(workspace in sdram )
BREAKMODE	SOFT			;Breakpoints are implemented by replacing code with a TRAP instruction
VECTOR		CATCH			;catch unhandled exceptions(the memory at address 0x00000000 to 
					;0x00001fff must is writable. 
DCACHE		FLUSH			;Before the BDI accesses any memory,the data cache is flushed and
					;only external memory is accessed.need a valid workspace for the flush code
MEMDELAY	4000			;add CPU access clocks for a slow (eg.boot ROM)memory 4000 cycles
;-------------------------------------------------
[HOST]
;opcode		opdata			comment						
;------------------------------------------------------------------------------------
;IP		ipaddress		;the IP address of the host
;FILE		filename		;the name of the program file
;FORMAT		format[offset]		;the format of the image file and an optionalload address offset
;LOAD		mode			;in Agent mode define if the code is loaded auto after every reset
;START		address			;the address where to start the program file
;DEBUGPORT	port			;TCP port GDB use to access the target
;PROMPT		string			;define a new Telnet prompt
;DUMP		filename		;the default file name used for the Telnet DUMP command
;TELNET		mode			;ECHO(default),NOECHO or LINE
;------------------------------------------------------------------------------------
;-------------------------------------------------
IP		192.168.0.133		;The IP of host PC is 192.168.0.188
LOAD		MANUAL			;load code MANUAL
DEBUGPORT	2001
PROMPT		tgl>	
;-------------------------------------------------
;
[FLASH]
;opcode		opdata			comment						
;------------------------------------------------------------------------------------
;FILE		configword.bin		;the file configword.bin will be program into the flash
;FORMAT		BIN[offset]		;file type to be progarmmed is BIN(SREC,BIN,AOUT,ELF or IMAGE)
;WORKSPACE	address			;use to program faster(at least 2Kbyte RAM(inter DRAM commonly)
;ERASE		address[mode]		;The flash memory may be individually erased via the Telnet interface.
					;In order to make erasing of multiple flash sectors easier,you can enter
					;an erase list.All entries in the erase list will be procesed if you enter 
					;ERASE at the Telnet prompt without any parameter.
					;address	Address of the flash sector,block or chip to erase 
					;mode		BLOCK,CHIP
					;Without this optional parameter,the BDI executes a sector	
					;erase.if supported by the chip,you can also specify a 
					;block or chip erase
					;Example:	ERASE 0X5040000;erase sector 4 of flash
					;ERASE 0X5060000;erase sector 6 of flash
					;ERASE 0X5000000 CHIP;erase whole chip(s)
;------------------------------------------------------------------------------------
;-------------------------------------------------
CHIPTYPE	MIRRORX16		;For 16bit only flash from AMD
CHIPSIZE	0x2000000		;The size of one flash chip in bytes=256(256Mbit)*1024*1024/8=33554432(D)
					;=2000000(H)
BUSWIDTH	32			;The width of the flash memory bus in bits is 32(8 | 16 | 32 | 64)
WORKSPACE	0xf0000000		;workspace in dual port ram
;-------------------------------------------------
;
[REGS]

DMM1		0xf0000000
FILE		reg8280.def
;-------------------------------------------------
;
;=======================================END=========================================