;SDRAM_END	EQU	0x034000000
_STACK_BASEADDRESS	EQU (SDRAM_END-0x8000)	;0x33ff8000
_MMUTT_STARTADDRESS	EQU (SDRAM_END-0x8000)	;0x33ff8000
_ISR_STARTADDRESS	EQU (SDRAM_END-0x100)	;0x33ffff00

		GBLL 	PLL_ON_START  
PLL_ON_START	SETL 	{TRUE}


		GBLL	ENDIAN_CHANGE
ENDIAN_CHANGE	SETL	{FALSE}

		GBLA	ENTRY_BUS_WIDTH
ENTRY_BUS_WIDTH	SETA	16	


;BUSWIDTH = 16,32
		GBLA    BUSWIDTH	;max. bus width for the GPIO configuration
BUSWIDTH	SETA    32


		GBLA	FCLK
FCLK		SETA	50000000

	[ FCLK = 50000000	
M_MDIV		EQU	0x5c	;Fin=12.0MHz Fout=50.0MHz
M_PDIV		EQU	0x4
M_SDIV		EQU	0x2
    	]

	END