//===============================================================================// 文 件 名：SPCE3200_Register.h// 功能描述：定義30個功能模塊的硬件寄存器//           這30個功能模塊包括：//               CLK-PLL\GPIO\WDOG\Sleep-Wakeup\INT\MIU\APBDMA\ADC\DAC//               \Timer\RTC-TMB\UART\SPI\I2C\SIO\SD-Card\NAND\NOR\LCD\other//               \CSI\TV\LDM\BLNDMA\I2S\USB\SFTCFG\MPEG4\DRAM// 維    護：by hongyan.Feng V1.0 2007.1.11//           by lijian       V2.0 2007.4.4    Fix spelling & Delete some registers//           by lijian       V2.1 2007.2.23   Add Buffer Clock Control Register//===============================================================================#ifndef _SPCE3200_REGISTER_H#define _SPCE3200_REGISTER_Htypedef volatile unsigned int UV32;//**************************************************************////                        CKG & PLL                             ////**************************************************************//#define P_CLK_CPU_SEL                       (UV32*)0x88210004#define P_CLK_AHB_CONF                      (UV32*)0x88210008#define P_CLK_AHB_SEL                       (UV32*)0x8821000C#define P_CLK_PLLV_CONF                     (UV32*)0x882100B4#define P_CLK_PLLV_SEL                      (UV32*)0x882100B8#define P_CLK_PLLAU_CONF                    (UV32*)0x882100bc#define P_CLK_32K_CONF                      (UV32*)0x88210114#define P_PLLV_STABLE_TIME                  (UV32*)0x88210104#define P_BUFCTRL_CLK_CONF                  (UV32*)0x882100C8//**************************************************************////                           GPIO                               ////**************************************************************//#define P_GPIO_CLK_CONF                     (UV32*)0x882100FC#define P_IOA_GPIO_SETUP                    (UV32*)0x88200038#define P_IOB_GPIO_SETUP                    (UV32*)0x8820004C#define P_IOB_GPIO_INPUT                    (UV32*)0x88200070#define P_IOA_GPIO_INPUT                    (UV32*)0x88200074#define P_IOA_GPIO_INT                      (UV32*)0x88200090//**************************************************************////                           SFTCFG                             ////**************************************************************//#define P_ROMCSN_INTERFACE_SEL              (UV32*)0x88200004#define P_DRAM_INTERFACE_SEL                (UV32*)0x88200008#define P_DRAM_GPIO_SETUP                   (UV32*)0x88200050#define P_DRAM_GPIO_INPUT                   (UV32*)0x88200070#define P_CLK_CPU2MPEG4_SEL                 (UV32*)0x882000C0//**************************************************************////                            WDOG                              ////**************************************************************//#define P_WDOG_CLK_CONF                     (UV32*)0x88210084#define P_WDOG_RESET_STATUS                 (UV32*)0x882100E8#define P_WDOG_MODE_CTRL                    (UV32*)0x88170000#define P_WDOG_CYCLE_SETUP                  (UV32*)0x88170004#define P_WDOG_CLR_COMMAND                  (UV32*)0x88170008//**************************************************************////                          Sleep-Wakeup                        ////**************************************************************//#define P_SLEEP_MODE_CTRL                   (UV32*)0x88210000#define P_SLEEP_CLK_SEL                     (UV32*)0x882100DC#define P_WAKEUP_KEYC_SEL                   (UV32*)0x88200008#define P_WAKEUP_KEYC_CLR                   (UV32*)0x882100C0//**************************************************************////                            INT                               ////**************************************************************//#define P_INT_CLK_CONF                      (UV32*)0x882100D0#define P_INT_REQ_STATUS1                   (UV32*)0x880a0000#define P_INT_REQ_STATUS2                   (UV32*)0x880a0004#define P_INT_GROUP_PRI                     (UV32*)0x880a0008#define P_INT_GROUP0_PRI                    (UV32*)0x880a0010#define P_INT_GROUP1_PRI                    (UV32*)0x880a0014#define P_INT_GROUP2_PRI                    (UV32*)0x880a0018#define P_INT_GROUP3_PRI                    (UV32*)0x880a001C#define P_INT_MASK_CTRL1                    (UV32*)0x880a0020#define P_INT_MASK_CTRL2                    (UV32*)0x880a0024//**************************************************************////                              MIU                             ////**************************************************************//#define P_MIU_CLK_CONF                      (UV32*)0x88210010#define P_MIU_SDRAM_POWER                   (UV32*)0x8807005C#define P_MIU_SDRAM_SETUP1                  (UV32*)0x88070060#define P_MIU_SDRAM_SETUP2                  (UV32*)0x88070094#define P_MIU_SDRAM_SETUP3                  (UV32*)0x88230060#define P_MIU_SDRAM_STATUS                  (UV32*)0x8807006C//**************************************************************////                            APBDMA                            ////**************************************************************//#define P_DMA_CLK_CONF                      (UV32*)0x88210058#define P_DMA_BUSY_STATUS                   (UV32*)0x88080000#define P_DMA_INT_STATUS                    (UV32*)0x88080004#define P_DMA_AHB_SA0BA                     (UV32*)0x88080008#define P_DMA_AHB_SA1BA                     (UV32*)0x8808000C#define P_DMA_AHB_SA2BA                     (UV32*)0x88080010#define P_DMA_AHB_SA3BA                     (UV32*)0x88080014#define P_DMA_AHB_EA0BA                     (UV32*)0x88080018#define P_DMA_AHB_EA1BA                     (UV32*)0x8808001C#define P_DMA_AHB_EA2BA                     (UV32*)0x88080020#define P_DMA_AHB_EA3BA                     (UV32*)0x88080024#define P_DMA_APB_SA0                       (UV32*)0x88080028#define P_DMA_APB_SA1                       (UV32*)0x8808002C#define P_DMA_APB_SA2                       (UV32*)0x88080030#define P_DMA_APB_SA3                       (UV32*)0x88080034#define P_DMA_AHB_SA0BB                     (UV32*)0x8808004C#define P_DMA_AHB_SA1BB                     (UV32*)0x88080050#define P_DMA_AHB_SA2BB                     (UV32*)0x88080054#define P_DMA_AHB_SA3BB                     (UV32*)0x88080058#define P_DMA_AHB_EA0BB                     (UV32*)0x8808005C#define P_DMA_AHB_EA1BB                     (UV32*)0x88080060#define P_DMA_AHB_EA2BB                     (UV32*)0x88080064#define P_DMA_AHB_EA3BB                     (UV32*)0x88080068#define P_DMA_CHANNEL0_CTRL                 (UV32*)0x8808006C#define P_DMA_CHANNEL1_CTRL                 (UV32*)0x88080070#define P_DMA_CHANNEL2_CTRL                 (UV32*)0x88080074#define P_DMA_CHANNEL3_CTRL                 (UV32*)0x88080078#define P_DMA_CHANNEL_RESET                 (UV32*)0x8808007C//**************************************************************////                           ADC                                ////**************************************************************//#define P_ADC_CLK_CONF                      (UV32*)0x882100AC#define P_ADC_CLK_SEL                       (UV32*)0x882100B0#define P_ADC_GPIO_SETUP                    (UV32*)0x88200048#define P_ADC_GPIO_INPUT                    (UV32*)0x88200078#define P_ADC_GPIO_INT                      (UV32*)0x8820009C#define P_ADC_AINPUT_CTRL                   (UV32*)0x88200054#define P_ADC_MIC_CTRL1                     (UV32*)0x881a0000#define P_ADC_MIC_GAIN                      (UV32*)0x881a0004#define P_ADC_SAMPLE_CLK                    (UV32*)0x881a0008#define P_ADC_SAMPLE_HOLD                   (UV32*)0x881a000c#define P_ADC_MIC_CTRL2                     (UV32*)0x881a0010#define P_ADC_INT_STATUS                    (UV32*)0x881a0014#define P_ADC_MANUAL_DATA                   (UV32*)0x881a0018#define P_ADC_AUTO_DATA                     (UV32*)0x881a001c#define P_ADC_MIC_DATA                      (UV32*)0x881a0020//**************************************************************////                           DAC                                ////**************************************************************//#define P_DAC_CLK_CONF                      (UV32*)0x8821003C#define P_DAC_FIFOBA_LOW                    (UV32*)0x88051080#define P_DAC_FIFOBA_HIGH                   (UV32*)0x88051084#define P_DAC_SAMPLE_CLK                    (UV32*)0x88051064#define P_DAC_INT_STATUS                    (UV32*)0x88051088#define P_DAC_MODE_CTRL1                    (UV32*)0x88051474#define P_DAC_MODE_CTRL2                    (UV32*)0x88051034#define P_DAC_OUTPUT_CH0                    (UV32*)0x88051040#define P_DAC_OUTPUT_CH1                    (UV32*)0x88051044//**************************************************************////                              Timer                           ////**************************************************************//#define P_TIMER_CLK_SEL                     (UV32*)0x882100E4#define P_TIMER_INTERFACE_SEL               (UV32*)0x88200010#define P_TIMER0_CLK_CONF                   (UV32*)0x8821006C#define P_TIMER0_MODE_CTRL                  (UV32*)0x88160000#define P_TIMER0_CCP_CTRL                   (UV32*)0x88160004#define P_TIMER0_PRELOAD_DATA               (UV32*)0x88160008#define P_TIMER0_CCP_DATA                   (UV32*)0x8816000C#define P_TIMER0_COUNT_DATA                 (UV32*)0x88160010#define P_TIMER1_CLK_CONF                   (UV32*)0x88210070#define P_TIMER1_MODE_CTRL                  (UV32*)0x88161000#define P_TIMER1_CCP_CTRL                   (UV32*)0x88161004#define P_TIMER1_PRELOAD_DATA               (UV32*)0x88161008#define P_TIMER1_CCP_DATA                   (UV32*)0x8816100C#define P_TIMER1_COUNT_DATA                 (UV32*)0x88161010#define P_TIMER2_CLK_CONF                   (UV32*)0x88210074#define P_TIMER2_MODE_CTRL                  (UV32*)0x88162000#define P_TIMER2_CCP_CTRL                   (UV32*)0x88162004#define P_TIMER2_PRELOAD_DATA               (UV32*)0x88162008#define P_TIMER2_CCP_DATA                   (UV32*)0x8816200C#define P_TIMER2_COUNT_DATA                 (UV32*)0x88162010#define P_TIMER3_CLK_CONF                   (UV32*)0x88210078#define P_TIMER3_MODE_CTRL                  (UV32*)0x88163000#define P_TIMER3_CCP_CTRL                   (UV32*)0x88163004#define P_TIMER3_PRELOAD_DATA               (UV32*)0x88163008#define P_TIMER3_CCP_DATA                   (UV32*)0x8816300C#define P_TIMER3_COUNT_DATA                 (UV32*)0x88163010#define P_TIMER4_CLK_CONF                   (UV32*)0x8821007C#define P_TIMER4_MODE_CTRL                  (UV32*)0x88164000#define P_TIMER4_CCP_CTRL                   (UV32*)0x88164004#define P_TIMER4_PRELOAD_DATA               (UV32*)0x88164008#define P_TIMER4_CCP_DATA                   (UV32*)0x8816400C#define P_TIMER4_COUNT_DATA                 (UV32*)0x88164010#define P_TIMER5_CLK_CONF                   (UV32*)0x88210080#define P_TIMER5_MODE_CTRL                  (UV32*)0x88165000#define P_TIMER5_CCP_CTRL                   (UV32*)0x88165004#define P_TIMER5_PRELOAD_DATA               (UV32*)0x88165008#define P_TIMER5_CCP_DATA                   (UV32*)0x8816500C#define P_TIMER5_COUNT_DATA                 (UV32*)0x88165010//**************************************************************////                           RTC                                ////**************************************************************//#define P_RTC_CLK_CONF                      (UV32*)0x88210088#define P_RTC_TIME_SEC                      (UV32*)0x88166000#define P_RTC_TIME_MIN                      (UV32*)0x88166004#define P_RTC_TIME_HOUR                     (UV32*)0x88166008#define P_RTC_ALM_SEC                       (UV32*)0x8816600C#define P_RTC_ALM_MIN                       (UV32*)0x88166010#define P_RTC_ALM_HOUR                      (UV32*)0x88166014#define P_RTC_MODE_CTRL                     (UV32*)0x88166018#define P_RTC_INT_STATUS                    (UV32*)0x8816601C//**************************************************************////                           TMB                                ////**************************************************************//#define P_TMB_CLK_CONF                      (UV32*)0x882100E0#define P_TMB_MODE_CTRL                     (UV32*)0x88166020#define P_TMB_INT_STATUS                    (UV32*)0x88166024#define P_TMB_RESET_COMMAND                 (UV32*)0x88166028//**************************************************************////                           UART                               ////**************************************************************//#define P_UART_CLK_CONF                     (UV32*)0x8821005C#define P_UART_INTERFACE_SEL                (UV32*)0x88200000#define P_UART_GPIO_SETUP                   (UV32*)0x88200040#define P_UART_GPIO_INPUT                   (UV32*)0x88200074#define P_UART_GPIO_INT                     (UV32*)0x88200094#define P_UART_MODE_CTRL                    (UV32*)0x88150008#define P_UART_BAUDRATE_SETUP               (UV32*)0x8815000C#define P_UART_TXRX_STATUS                  (UV32*)0x88150010#define P_UART_ERR_STATUS                   (UV32*)0x88150004#define P_UART_TXRX_DATA                    (UV32*)0x88150000#define P_UART_WAKEUP_STATUS                (UV32*)0x88210110