//===============================================================================// 文 件 名：SPCE3200_Constant.h// 功能描述：定義22個(gè)功能模塊硬件寄存器中的常量//           這22個(gè)功能模塊包括：//               CLK-PLL\GPIO\WDOG\Sleep-Wakeup\INT\MIU\APBDMA\ADC//               \Timer\RTC-TMB\UART\SPI\I2C\SIO\SD-Card\NAND\LCD\TV//               \DAC\CSI\BLNDMA\MPEG4// 維    護(hù)：by hongyan.Feng V1.0 2007.1.11//           by lijian       V2.0 2007.4.4    Add Constants of 5 Advanced Modules//===============================================================================#ifndef _SPCE3200_CONSTANT_H#define _SPCE3200_CONSTANT_H//******************************************************************////                            CLK-PLL                               ////******************************************************************//#define C_CPU_CLK_PLLVDIV1        0x00000000    // P_CLK_CPU_SEL#define C_CPU_CLK_PLLVDIV2        0x00000001    // P_CLK_CPU_SEL#define C_CPU_CLK_PLLVDIV3        0x00000002    // P_CLK_CPU_SEL#define C_CPU_CLK_PLLVDIV4        0x00000003    // P_CLK_CPU_SEL#define C_CPU_CLK_PLLVDIV6        0x00000004    // P_CLK_CPU_SEL#define C_CPU_CLK_PLLVDIV8        0x00000005    // P_CLK_CPU_SEL#define C_CPU_CLK_PLLADIV1        0x00000006    // P_CLK_CPU_SEL#define C_CPU_CLK_PLLADIV2        0x00000007    // P_CLK_CPU_SEL#define C_CPU_CLK_PLLADIV3        0x00000008    // P_CLK_CPU_SEL#define C_CPU_CLK_PLLADIV4        0x00000009    // P_CLK_CPU_SEL#define C_CPU_CLK_PLLADIV6        0x0000000A    // P_CLK_CPU_SEL#define C_CPU_CLK_PLLADIV8        0x0000000B    // P_CLK_CPU_SEL#define C_AHB_CLK_EN              0x00000001    // P_CLK_AHB_CONF#define C_AHB_CLK_CPUDIV1         0x00000000    // P_CLK_AHB_SEL#define C_AHB_CLK_CPUDIV2         0x00000001    // P_CLK_AHB_SEL#define C_AHB_CLK_CPUDIV3         0x00000002    // P_CLK_AHB_SEL#define C_AHB_CLK_CPUDIV4         0x00000003    // P_CLK_AHB_SEL#define C_PLLV_CLK_EN             0x00000001    // P_CLK_PLLV_CONF#define C_PLLV_CLK_81M            0x00000003    // P_CLK_PLLV_SEL#define C_PLLV_CLK_87M            0x00000004    // P_CLK_PLLV_SEL#define C_PLLV_CLK_97M            0x00000005    // P_CLK_PLLV_SEL#define C_PLLV_CLK_101M           0x00000006    // P_CLK_PLLV_SEL#define C_PLLV_CLK_108M           0x00000007    // P_CLK_PLLV_SEL#define C_PLLV_CLK_114M           0x00000008    // P_CLK_PLLV_SEL#define C_PLLV_CLK_121M           0x00000009    // P_CLK_PLLV_SEL#define C_PLLV_CLK_128M           0x0000000A    // P_CLK_PLLV_SEL#define C_PLLV_CLK_135M           0x0000000B    // P_CLK_PLLV_SEL#define C_PLLV_CLK_141M           0x0000000C    // P_CLK_PLLV_SEL#define C_PLLV_CLK_148M           0x0000000D    // P_CLK_PLLV_SEL#define C_PLLV_CLK_155M           0x0000000E    // P_CLK_PLLV_SEL#define C_PLLV_CLK_162M           0x0000000F    // P_CLK_PLLV_SEL#define C_PLLA_CLK_EN             0x00000001    // P_CLK_PLLAU_CONF#define C_PLLA_CLK_73M            0x00000000    // P_CLK_PLLAU_CONF#define C_PLLA_CLK_67M            0x00000002    // P_CLK_PLLAU_CONF#define C_PLLU_CLK_EN             0x00000004    // P_CLK_PLLAU_CONF#define C_LVR_RST_EN              0x00000001    // P_LVR_RESET_CTRL#define C_32K_CRY_EN              0x00000001    // P_CLK_32K_CONF//******************************************************************////                               GPIO                               ////******************************************************************//#define C_IOA0_INTRISE_EN         0x00000001    // P_GPIO_PORT_INT#define C_IOA1_INTRISE_EN         0x00000002    // P_GPIO_PORT_INT#define C_IOA0_INTFALL_EN         0x00000100    // P_GPIO_PORT_INT#define C_IOA1_INTFALL_EN         0x00000200    // P_GPIO_PORT_INT#define C_IOA0_INTRISE_FLAG       0x00010000    // P_GPIO_PORT_INT#define C_IOA1_INTRISE_FLAG       0x00020000    // P_GPIO_PORT_INT#define C_IOA0_INTFALL_FLAG       0x01000000    // P_GPIO_PORT_INT#define C_IOA1_INTFALL_FLAG       0x02000000    // P_GPIO_PORT_INT#define C_GPIO_CLK_EN             0x00000001    // P_GPIO_CLK_CONF#define C_GPIO_RST_DIS            0x00000002    // P_GPIO_CLK_CONF//******************************************************************////                              WDOG                                ////******************************************************************//#define C_WDOG_CLK_EN             0x00000001    // P_WDOG_CLK_CONF#define C_WDOG_RST_DIS            0x00000002    // P_WDOG_CLK_CONF#define C_WDOG_ERR_FLAG           0x00000001    // P_WDOG_RESET_STATUS#define C_WDOG_RST_FLAG           0x00000002    // P_WDOG_RESET_STATUS#define C_WDOG_CTRL_EN            0x80000000    // P_WDOG_MODE_CTRL#define C_WDOG_CLR_COMMAND        0xa0000005    // P_WDOG_CLR_COMMAND//******************************************************************////                           Sleep-Wakeup                           ////******************************************************************//#define C_SLEEP_WAIT_MODE         0x00000005    // P_SLEEP_MODE_CTRL#define C_SLEEP_HALT_MODE         0x0000000B    // P_SLEEP_MODE_CTRL#define C_SLEEP_CLK_PLLVDIV8      0x00000000    // P_SLEEP_CLK_SEL#define C_SLEEP_CLK_32K           0x00000001    // P_SLEEP_CLK_SEL#define C_WAKEUP_KEY_GROUP1       0x00000001    // P_WAKEUP_KEYC_SEL#define C_WAKEUP_KEY_GROUP2       0x00000002    // P_WAKEUP_KEYC_SEL#define C_WAKEUP_KEY_GROUP3       0x00000003    // P_WAKEUP_KEYC_SEL#define C_WAKEUP_KEY_GROUP4       0x00000004    // P_WAKEUP_KEYC_SEL#define C_WAKEUP_KEY_GROUP5       0x00000005    // P_WAKEUP_KEYC_SEL#define C_WAKEUP_KEY_CLR          0x00000000    // P_WAKEUP_KEYC_CLR#define C_WAKEUP_KEY_EN           0x00000001    // P_WAKEUP_KEYC_CLR//******************************************************************////                              INT                                 ////******************************************************************//#define C_INT_RST_DIS             0x00000001    // P_INT_CLK_CONF#define C_INT_DAC_REQ             0x00000001    // P_INT_REQ_STATUS1#define C_INT_MIC_REQ             0x00000010    // P_INT_REQ_STATUS1#define C_INT_ADC_REQ             0x00000020    // P_INT_REQ_STATUS1#define C_INT_TMB_REQ             0x00000040    // P_INT_REQ_STATUS1#define C_INT_TIMER_REQ           0x00000080    // P_INT_REQ_STATUS1#define C_INT_LCDVS_REQ           0x00000200    // P_INT_REQ_STATUS1#define C_INT_USB_REQ             0x00040000    // P_INT_REQ_STATUS1#define C_INT_SIO_REQ             0x00080000    // P_INT_REQ_STATUS1#define C_INT_SPI_REQ             0x00100000    // P_INT_REQ_STATUS1#define C_INT_UART_REQ            0x00200000    // P_INT_REQ_STATUS1#define C_INT_NAND_REQ            0x00400000    // P_INT_REQ_STATUS1#define C_INT_SD_REQ              0x00800000    // P_INT_REQ_STATUS1#define C_INT_I2C_REQ             0x01000000    // P_INT_REQ_STATUS1#define C_INT_I2S_REQ             0x02000000    // P_INT_REQ_STATUS1#define C_INT_APBCH0_REQ          0x04000000    // P_INT_REQ_STATUS1#define C_INT_APBCH1_REQ          0x08000000    // P_INT_REQ_STATUS1#define C_INT_LDM_REQ             0x10000000    // P_INT_REQ_STATUS1#define C_INT_BLN_REQ             0x20000000    // P_INT_REQ_STATUS1#define C_INT_APBCH2_REQ          0x40000000    // P_INT_REQ_STATUS1#define C_INT_APBCH3_REQ          0x80000000    // P_INT_REQ_STATUS1#define C_INT_RTC_REQ             0x00000001    // P_INT_REQ_STATUS2#define C_INT_MP4_REQ             0x00000002    // P_INT_REQ_STATUS2#define C_INT_ECC_REQ             0x00000004    // P_INT_REQ_STATUS2#define C_INT_GPIO_REQ            0x00000008    // P_INT_REQ_STATUS2#define C_INT_DAC_DIS             0x00000001    // P_INT_MASK_CTRL1#define C_INT_MIC_DIS             0x00000010    // P_INT_MASK_CTRL1#define C_INT_ADC_DIS             0x00000020    // P_INT_MASK_CTRL1#define C_INT_TMB_DIS             0x00000040    // P_INT_MASK_CTRL1#define C_INT_TIMER_DIS           0x00000080    // P_INT_MASK_CTRL1#define C_INT_LCDVS_DIS           0x00000200    // P_INT_MASK_CTRL1#define C_INT_FRAME_END           0x00001000    // P_INT_MASK_CTRL1#define C_INT_POS_HIT             0x00002000    // P_INT_MASK_CTRL1#define C_INT_MD_FRAME            0x00004000    // P_INT_MASK_CTRL1#define C_INT_TG_CAPACK           0x00008000    // P_INT_MASK_CTRL1#define C_INT_TG_OF               0x00008000    // P_INT_MASK_CTRL1#define C_INTI_MD_UF              0x00008000    // P_INT_MASK_CTRL1#define C_INT_FRAME_DIS           0x00008000    // P_INT_MASK_CTRL1#define C_INT_USB_DIS             0x00040000    // P_INT_MASK_CTRL1#define C_INT_SIO_DIS             0x00080000    // P_INT_MASK_CTRL1#define C_INT_SPI_DIS             0x00100000    // P_INT_MASK_CTRL1#define C_INT_UART_DIS            0x00200000    // P_INT_MASK_CTRL1#define C_INT_NAND_DIS            0x00400000    // P_INT_MASK_CTRL1#define C_INT_SD_DIS              0x00800000    // P_INT_MASK_CTRL1#define C_INT_I2C_DIS             0x01000000    // P_INT_MASK_CTRL1#define C_INT_I2S_DIS             0x02000000    // P_INT_MASK_CTRL1#define C_INT_APBCH0_DIS          0x04000000    // P_INT_MASK_CTRL1#define C_INT_APBCH1_DIS          0x08000000    // P_INT_MASK_CTRL1#define C_INT_LDM_DIS             0x10000000    // P_INT_MASK_CTRL1#define C_INT_BLN_DIS             0x20000000    // P_INT_MASK_CTRL1#define C_INT_APBCH2_DIS          0x40000000    // P_INT_MASK_CTRL1#define C_INT_APBCH3_DIS          0x80000000    // P_INT_MASK_CTRL1#define C_INT_RTC_DIS             0x00000001    // P_INT_MASK_CTRL2#define C_INT_MP4_DIS             0x00000002    // P_INT_MASK_CTRL2#define C_INT_ECC_DIS             0x00000004    // P_INT_MASK_CTRL2#define C_INT_GPIO_DIS            0x00000008    // P_INT_MASK_CTRL2//******************************************************************////                              MIU                                 ////******************************************************************//#define C_MIU_RST_DIS             0x00000004    // P_MIU_CLK_CONF#define C_MIU_CLK_EN              0x00000003    // P_MIU_CLK_CONF#define C_MIU_REFLASH_DIS         0x00000002    // P_MIU_CLK_CONF#define C_MIU_REFLASH_EN          0x00000001    // P_MIU_CLK_CONF#define C_SDRAM_DEEP_DOWN         0x00000008    // P_MIU_SDRAM_POWER#define C_SDRAM_MRS_REDO          0x00000004    // P_MIU_SDRAM_POWER#define C_SDRAM_POWER_DOWN        0x00000002    // P_MIU_SDRAM_POWER#define C_SDRAM_SELF_REFRESH      0x00000001    // P_MIU_SDRAM_POWER#define C_SDRAM_TRP_1CYCLE        0x00000000    // P_MIU_SDRAM_SETUP1#define C_SDRAM_TRP_2CYCLE        0x00000001    // P_MIU_SDRAM_SETUP1#define C_SDRAM_TRCD_1CYCLE       0x00000000    // P_MIU_SDRAM_SETUP1#define C_SDRAM_TRCD_2CYCLE       0x00000002    // P_MIU_SDRAM_SETUP1#define C_SDRAM_CAS_2CYCLE        0x00000000    // P_MIU_SDRAM_SETUP1#define C_SDRAM_CAS_3CYCLE        0x00000004    // P_MIU_SDRAM_SETUP1#define C_SDRAM_WORD_8BIT         0x00000000    // P_MIU_SDRAM_SETUP1#define C_SDRAM_WORD_16BIT        0x01000000    // P_MIU_SDRAM_SETUP1#define C_SDRAM_WORD_32BIT        0x02000000    // P_MIU_SDRAM_SETUP1#define C_SDRAM_ROW_1024          0x00000000    // P_MIU_SDRAM_SETUP1#define C_SDRAM_ROW_2048          0x04000000    // P_MIU_SDRAM_SETUP1#define C_SDRAM_ROW_4096          0x08000000    // P_MIU_SDRAM_SETUP1#define C_SDRAM_ROW_8192          0x0C000000    // P_MIU_SDRAM_SETUP1#define C_MIU_CTRL_EN             0x80000000    // P_MIU_SDRAM_SETUP1#define C_MIU_OFF_STATUS          0x00000001    // P_MIU_SDRAM_STATUS#define C_SDRAM_TRP_3CYCLE        0x00000001    // P_MIU_SDRAM_SETUP2#define C_SDRAM_TRCD_3CYCLE       0x00000002    // P_MIU_SDRAM_SETUP2//******************************************************************////                            APBDMA                                ////******************************************************************//#define C_DMA_CLK_EN              0x00000001    // P_DMA_CLK_CONF#define C_DMA_RST_DIS             0x00000002    // P_DMA_CLK_CONF#define C_DMA_CH0_BUSY            0x00000001    // P_DMA_BUSY_STATUS#define C_DMA_CH1_BUSY            0x00000002    // P_DMA_BUSY_STATUS