;; This is McBSP test program. The work-mode of McBSP Series:
;;      BLD=1 (Digital loop back mode enabled)  
;;      RCOMPAND=10 or 11 (u-law/A-law Expand: 8bits -> 16bits)
;;      (R/X)INTM=00 (generate an interrupt every word traxsmitted)
;;      ar3 -> Transmit data buffer(buffer_1)
;;      ar4 -> receive data buffer(buffer_2)
;; The program is applicable for VC54xx 
;; Designed by liyubai
;; Modifing 1.0    Time 2001,6,28

		.title "Test McBSP Program"
		.mmregs
		.global _c_int00,buffer_1,buffer_2
		.global interrupt_vector
drr11		.set 41h		;McBSP1 receive data register
dxr11		.set 43h		;McBSP1 transmit data register
spsa1		.set 48h		;McBSP1 sub_bank address register
spcd1		.set 49h		;McBSP1 sub_bank data register
		.bss stack_memory,500
		.bss buffer_1,1000
		.bss buffer_2,1000
interrupt_vector:			;interrupt vector table
		.text
rs		b  _c_int00
                nop
		nop
nmi     	b __ret
        	.word   0,0
sint17  	b __ret
        	.word   0,0
sint18  	b __ret
        	.word   0,0
sint19  	b __ret
        	.word   0,0
sint20  	b __ret
        	.word   0,0
sint21  	b __ret
        	.word   0,0
sint22  	b __ret
        	.word   0,0
sint23  	b __ret
        	.word   0,0
sint24  	b __ret
        	.word   0,0
sint25  	b __ret
        	.word   0,0
sint26  	b __ret
        	.word   0,0
sint27  	b __ret
        	.word   0,0
sint28  	b __ret
        	.word   0,0
sint29  	b __ret
        	.word   0,0
sint30  	b __ret
        	.word   0,0
int0  		b __ret
        	.word   0,0
int1  		b __ret
        	.word   0,0
int2  		b __ret
        	.word   0,0
tint      	b __ret
        	.word   0,0
brint0  	b __ret
        	.word   0,0
bxint0    	b __ret
        	.word   0,0
dmac0     	b __ret
        	.word   0,0
dmac1     	b __ret
        	.word   0,0
int3      	b __ret
        	.word   0,0
hpint     	b __ret
        	.word   0,0
brint1  	b McBSP1_receive_int
		nop
		nop
bxint1  	b McBSP1_transmit_int
		nop
		nop
q28     	.word 0,0,0,0
q29     	.word 0,0,0,0
q30     	.word 0,0,0,0
q31     	.word 0,0,0,0

_c_int00: 
		ssbx intm		  ;close all interrupt
		stm #0ffffh,ifr	  ;cleare all interrupt_flag

		stm  #stack_memory+500,sp  	;sp => stack_memory
   		stm  #20a0h,pmst    	;vector table start: 0x2080
		call Clear_McBSP1_receive_buf
     	call McBSP1_initializing
		
		stm #buffer_1,ar3
		stm #buffer_2,ar4
		ld #1000,b		;pre_put numberS of McBSP interrupt
		stm  #0c00h,imr		;enable RINT1,XINT1
		rsbx intm		;enable all int
wait_McBSP_int:
		nop
		nop
		bc wait_McBSP_int,bneq
		nop
		nop
		ssbx intm       ; close all int !
		b $
		nop

__ret:		nop
		rete
;------------------------------------------------------------
; Init setup Mcbsp1 !
;------------------------------------------------------------
McBSP1_initializing:
		stm #0,spsa1		;choose SPCR11
		stm #0a000h,spcd1	;1010000000000000 => SPCR11. 
					;DLB(15)=1(Digital loop back moden enabled)
					;RJUST(14-13)=01;CLKSTP(12-11)=00
					;RES(10-8)=000,DXENA(7)=0,ABIS(6)=0
					;RINTM(5-4)=00,RSYNCERR(3)=0,RFULL(2)=0
					;RRDY(1)=0,RRST(0)=0
		stm #1,spsa1		;choose spcr21
		stm #100h,spcd1		;0000000100000000 => SPCR21.
					;RES(15-10)=000000,FREE(9)=0,SOFT(8)=1
					;FRST(7)=0,GRST(6)=0,XINT(5-4)=00,XSYNCERR(3)=0
					;XFULL(2)=0,XRDY(1)=0,XRST(0)=0
		stm #2,spsa1		;choose RCR11
		stm #0,spcd1		;0000000000000000 => RCR11.
					;RES(15)=0,RFRLEN1(14-8)=000 0000
					;RWDLEN1(7-5)=000,RES(4-0)=0 0000
		stm #3,spsa1		;choose RCR21
		stm #00H,spcd1		;0000000000010000 => RCR21.
					;RPHASE(15)=0,RFRLEN2(14-8)=000 0000
					;RWDLEN2(7-5)=000,RCOMPAND(4-3)=10(u-law EXPAND)
					;RFIG(2)=0,RDATDLY(1-0)=00
		stm #4,spsa1		;choose XCR11
		stm #0h,spcd1		;0000000000000000 => XCR11.
					;RES(15)=0,XFRLEN1(14-8)=000 0000
					;XWDLEN1(7-5)=000,RES(4-0)=0 0000
		stm #5,spsa1		;choose XCR21
		stm #10h,spcd1		;0000000000000000 => XCR21.
					;XPHASE(15)=0,XFRLEN2(14-8)=000 0000
					;XWDLEN2(7-5)=000,XCOMPAND(4-3)=10(No compand)
					;XFIG(2)=0,XDATDLY(1-0)=00
		stm #6,spsa1		;choose SRGR11
		stm #1c8h,spcd1		;0000000100001111 => SRGR11 (100M/200=500k)
					;FWID(15-8)=0000 0001,CLKGDV(7-0)=1100 1000
		stm #7,spsa1		;choose SRGR21
		stm #02000H,spcd1	;0010000000000000 => SRGR21
					;GSYNC(15)=0,CLKSP(14)=0,CLKSM(13)=1(use CPU_clk)
					;FSGM(12)=0(1->Internal SRG generate Transmit FS)
					;FPER(11-0)=0000 0000 0000
		stm #0eh,spsa1		;choose PCR1
		stm #0a0eh,spcd1		;0000101000001110 => PCR1
					;RES(15-14)=00,XIOEN(13)=0,RIOEN(12)=0
					;FSXM(11)=1,FSRM(10)=0,CLKXM(9)=1,CLKRM(8)=0
					;RES(7)=0,CLKS_STAT(6)=0,DX_STAT(5)=0,RX_STAT(4)=0
					;FSXP(3)=1,FSRP(2)=1,CLKXP(1)=1,CLKRP(0)=0
		rpt #0ffh
		nop
		
		stm #0,spsa1		;choose SPCR11
		stm #0a001h,spcd1	;1010000000000001 => SPCR11. 
					;McBSP1 receive enabled. 
		stm #1,spsa1		;choose spcr21
		stm #1c1h,spcd1		;0000000111000001 => SPCR21.
					;McBSP1 sample rate generator,transmit enabled. 
		nop
		stm #0ffh,dxr11		;first data writed to dxr11
		nop
		ret
;----------------------------------------------------------
;  clear receive buffer(buffer_1), and init send buffer
;---------------------------------------------------------
Clear_McBSP1_receive_buf:
		stm #buffer_2,ar4         
		nop
		nop
		rpt #999
		st #0,*ar4+ 
		
		stm #999,brc
		stm #buffer_1,ar4
		nop
		nop
		xor a             ; A=0
		rptb  s_buf1
		stl  a,*ar4+
        add #2h,a
s_buf1:        
		nop
	    nop
		ret
;------------------------------------------------------------
; Mcbsp1 receive  program !
;------------------------------------------------------------
McBSP1_receive_int:  
        pshm st0
        pshm st1
        ld #0,dp
		sub #1,b  
		xor a
		sub drr11,a  
;		and #0ffh,a
;	    xor #055h,a
        
		stl a,*ar4+
		nop 
		popm st1
		popm st0
		rete
;------------------------------------------------------------
; Mcbsp1 receive  program !
;------------------------------------------------------------
McBSP1_transmit_int:
		ld *ar3+,a
		stlm a,dxr11
		nop
		rete
		.end