#ifndef CYGONCE_HAL_PLF_INTR_H#define CYGONCE_HAL_PLF_INTR_H//==========================================================================////      plf_intr.h////      Spce3200 Platform Interrupt and clock support////==========================================================================//####ECOSGPLCOPYRIGHTBEGIN####// -------------------------------------------// This file is part of eCos, the Embedded Configurable Operating System.// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.//// eCos is free software; you can redistribute it and/or modify it under// the terms of the GNU General Public License as published by the Free// Software Foundation; either version 2 or (at your option) any later version.//// eCos is distributed in the hope that it will be useful, but WITHOUT ANY// WARRANTY; without even the implied warranty of MERCHANTABILITY or// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License// for more details.//// You should have received a copy of the GNU General Public License along// with eCos; if not, write to the Free Software Foundation, Inc.,// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.//// As a special exception, if other files instantiate templates or use macros// or inline functions from this file, or you compile this file and link it// with other works to produce a work based on this file, this file does not// by itself cause the resulting work to be covered by the GNU General Public// License. However the source code for this file must still be made available// in accordance with section (3) of the GNU General Public License.//// This exception does not invalidate any other reasons why a work based on// this file might be covered by the GNU General Public License.//// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.// at http://sources.redhat.com/ecos/ecos-license/// -------------------------------------------//####ECOSGPLCOPYRIGHTEND####//==========================================================================//#####DESCRIPTIONBEGIN####//// Author(s):    whhhh// Contributors: whhhh//				 lijian// Date:         2007-11-26// Purpose:      Define Interrupt support// Description:  The macros defined here provide the HAL APIs for handling//               interrupts and the clock for the Spce3200 demo board.//              // Usage://              #include <cyg/hal/plf_intr.h>//              ...//              ////####DESCRIPTIONEND####////==========================================================================#include <pkgconf/hal.h>#include <cyg/infra/cyg_type.h>//--------------------------------------------------------------------------// No platform specific stuff at present.//--------------------------------------------------------------------------#ifndef CYGHWR_HAL_RESET_DEFINED#define CYGHWR_HAL_RESET_DEFINED#define HAL_PLATFORM_RESET()      //#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000#define HAL_PLATFORM_RESET_ENTRY 0x9f000000#endif // CYGHWR_HAL_RESET_DEFINED#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED#define CYGNUM_HAL_INTERRUPT_ADCOVERFLOW         59#define CYGNUM_HAL_INTERRUPT_ADCGP               58#define CYGNUM_HAL_INTERRUPT_TIMERBASE           57#define CYGNUM_HAL_INTERRUPT_TIMER               56#define CYGNUM_HAL_INTERRUPT_TVVBLANK            55#define CYGNUM_HAL_INTERRUPT_LCDVBLANK           54#define CYGNUM_HAL_INTERRUPT_LGUN                52#define CYGNUM_HAL_INTERRUPT_SENSORFEND          51#define CYGNUM_HAL_INTERRUPT_SENSORCORHIT        50#define CYGNUM_HAL_INTERRUPT_SENSORMFEND         49#define CYGNUM_HAL_INTERRUPT_SENSORCAP           48#define CYGNUM_HAL_INTERRUPT_TVCORHIT            47#define CYGNUM_HAL_INTERRUPT_USB                 45#define CYGNUM_HAL_INTERRUPT_SIO                 44#define CYGNUM_HAL_INTERRUPT_SPI                 43#define CYGNUM_HAL_INTERRUPT_UART                42#define CYGNUM_HAL_INTERRUPT_NAND                41#define CYGNUM_HAL_INTERRUPT_SD                  40#define CYGNUM_HAL_INTERRUPT_IICM                39#define CYGNUM_HAL_INTERRUPT_IICS                38#define CYGNUM_HAL_INTERRUPT_DMACH1              37#define CYGNUM_HAL_INTERRUPT_DMACH2              36#define CYGNUM_HAL_INTERRUPT_LDMDMA              35#define CYGNUM_HAL_INTERRUPT_BLNDMA              34#define CYGNUM_HAL_INTERRUPT_DMACH3              33#define CYGNUM_HAL_INTERRUPT_DMACH4              32#define CYGNUM_HAL_INTERRUPT_ALARM               31#define CYGNUM_HAL_INTERRUPT_MP4                 30#define CYGNUM_HAL_INTERRUPT_C3                  29#define CYGNUM_HAL_INTERRUPT_GPIO                28#define CYGNUM_HAL_INTERRUPT_BUFCTL              27#define CYGNUM_HAL_INTERRUPT_REV1                26#define CYGNUM_HAL_INTERRUPT_REV2                25#define CYGNUM_HAL_INTERRUPT_REV3                24// Min/Max ISR numbers and how many there are#define CYGNUM_HAL_ISR_MIN                     0#define CYGNUM_HAL_ISR_MAX                     63 /* CWWeng 2006/6/15 : 5 -> 63 */#define CYGNUM_HAL_ISR_HALF                    32 /* WHHHH 2007/6/15 : 5 -> 63 */#define CYGNUM_HAL_ISR_COUNT                   64 /* CWWeng 2006/6/15 : 6 -> 64 */// The vector used by the Real time clock. The default here is to use// interrupt 5, which is connected to the counter/comparator registers// in many MIPS variants.#ifndef CYGNUM_HAL_INTERRUPT_RTC#define CYGNUM_HAL_INTERRUPT_RTC            CYGNUM_HAL_INTERRUPT_TIMER#endif#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED#endif#endif // ifndef CYGONCE_HAL_PLF_INTR_H// End of plf_intr.h