?? run.syn.scr
字號:
analyze -format vhdl -lib WORK binary.vhdelaborate CFG_BINARY_BLOCK_BEHAVIORAL -lib DEFAULT -updatewrite -f db -h -o ../db/binary.read.dbset_operating_conditions -library "class" "WCCOM"set_wire_load "10x10"set_driving_cell -cell AN2P -library class all_inputs()set_load 1 all_outputs()compile -map_effort low/*include set_switching_activity.scr*/include set_switching_activity.tv.scrset_switching_activity -period 20 -toggle_rate 2 -static_prob 0.5 find(port,"clk")/*report power for the design */report_power report_power -netreport_power -cellwrite -f db -h -o ../db/binary.compiled.db/*quit*/
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