Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity RIPPLE is      Port ( clk : In    std_logic;             reset : In    std_logic;             count : BUFFER UNSIGNED (3 downto 0)); end RIPPLE; architecture BEHAVIORAL of RIPPLE is	signal count0, count1, count2 : std_logic;	begin	process(count)	begin	count0 <= count(0);	count1 <= count(1);	count2 <= count(2);	end process;	process(reset,clk)	begin	if (reset = '0') then		count(0) <= '0';	elsif (clk'event and clk = '1')then		if (count(0) = '1') then			count(0) <= '0';		else			count(0) <= '1';		end if;	end if;	end process;	process(reset,count0)	begin	if (reset = '0') then		count(1) <= '0';	elsif (count0'event and count0 = '1')then		if (count(1) = '1') then			count(1) <= '0';		else			count(1) <= '1';		end if;	end if;	end process;	process(reset,count1)	begin	if (reset = '0') then		count(2) <= '0';	elsif (count1'event and count1 = '1')then		if (count(2) = '1') then			count(2) <= '0';		else			count(2) <= '1';		end if;	end if;	end process;	process(reset,count2)	begin	if (reset = '0') then		count(3) <= '0';	elsif (count2'event and count2 = '1')then		if (count(3) = '1') then			count(3) <= '0';		else			count(3) <= '1';		end if;	end if;	end process; end BEHAVIORAL;configuration CFG_RIPPLE_BLOCK_BEHAVIORAL of RIPPLE is        for BEHAVIORAL         end for; end CFG_RIPPLE_BLOCK_BEHAVIORAL;