;******************************************************************************
;   MSP430x24x Demo - LFXT1 Oscillator Fault Detection
;
;   Description: System runs normally in LPM3 with Timer A clocked by
;   32kHz ACLK with a 1 second interrupt.  P1.0 is normally toggled every
;   1 second inside timer interrupt.  If an LFXT1 oscllator fault occurs,
;   NMI is requested forcing exit from LPM3. P1.0 is toggled rapidly by software
;   as long as LFXT1 osciallator fault is present.  Assumed only LFXT1 as NMI
;   source - code does not check for other NMI sources.
;   ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz
;   //* An external watch crystal between XIN & XOUT is required for ACLK *//	
;
;                MSP430x249
;             -----------------
;         /|\|              XIN|-
;          | |                 | 32kHz
;          --|RST          XOUT|-
;            |                 |
;            |             P1.0|-->LED
;
;   P.Thanigai
;   Texas Instruments Inc.
;   November 2007
;   Built with IAR Embedded Workbench Version: 3.42A
;******************************************************************************

#include  <msp430x24x.h>
;-------------------------------------------------------------------------------
            RSEG    CSTACK                  ; Define stack segment
;-------------------------------------------------------------------------------
            RSEG    CODE                    ; Assemble to Flash memory
;-----------------------------------------------------------------------------
RESET       mov.w   #SFE(CSTACK),SP         ; Initialize stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
SetupP1     bis.b   #001h,&P1DIR            ; P1.0 = output direction

SetupTA     mov.w   #CCIE,&TACCTL0          ; TACCR0 interrupt enabled
            mov.w   #32767,&TACCR0
            mov.w   #TASSEL_1+MC_1,&TACTL   
            
; An immedate Osc Fault will occur next
            bis.b   #OFIE,&IE1              ; Enable osc fault interrupt
                                            ;						
Mainloop    bis.w   #LPM3+GIE,SR            ; Enter LPM3, enable interrupts
            xor.b   #001h,&P1OUT            ; Toggle P1.0
            jmp     Mainloop                ;
                                            ;
;------------------------------------------------------------------------------
NMI_ISR;   Only osc fault enabled, R15 used temporarily and not saved
;          Assumed LFXT1 is only source for NMI interrupt
;------------------------------------------------------------------------------
CheckOsc    bic.b   #OFIFG,&IFG1            ; Clear OSC fault flag
            xor.b   #001h,&P1OUT            ; Toggle P1.0
            mov.w   #03FFFh,R15             ; R15 = Delay
CheckOsc1   dec.w   R15                     ; Time for flag to set
            jnz     CheckOsc1               ;
            bit.b   #OFIFG,&IFG1            ; OSC fault flag set?
            jnz     CheckOsc                ; OSC Fault, clear flag again
            bis.b   #OFIE,&IE1              ; re-enable osc fault interrupt
            reti                            ; return from interrupt
                                            ;
;------------------------------------------------------------------------------
TA_ISR;     
;------------------------------------------------------------------------------
            xor.b   #001h,&P1OUT            ; Toggle P1.0
            reti                            ;		
                                            ;
;-----------------------------------------------------------------------------
            COMMON  INTVEC                  ; Interrupt Vectors
;-----------------------------------------------------------------------------
            ORG     RESET_VECTOR            ; RESET Vector
            DW      RESET                   ;
            ORG     TIMERA0_VECTOR          ; Basic Timer Vector
            DW      TA_ISR                  ;
            ORG     NMI_VECTOR              ; NMI vector
            DW      NMI_ISR                 ;
            END