?? msp430x24x_uscia0_uart_07_9600.s43
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;*******************************************************************************
; MSP430x24x Demo - USCI_A0, Ultra-Low Pwr UART 9600 RX/TX, 32kHz ACLK
;
; Description: This program demonstrates a full-duplex 9600-baud UART using
; USCI_A0 and a 32kHz crystal. The program will wait in LPM3, and receive
; a string1 into RAM starting at 200h, and echo back the complete string.
; ACLK = BRCLK = LFXT1 = 32768, MCLK = SMCLK = DCO ~1.045MHz
; Baud rate divider with 32768Hz XTAL @9600 = 32768Hz/9600 = 3.41
; //* An external watch crystal is required on XIN XOUT for ACLK *//
;
; MSP430F249
; -----------------
; /|\| XIN|-
; | | | 32kHz
; --|RST XOUT|-
; | |
; | P3.4/UCA0TXD|------------>
; | | 9600 - 8N1
; | P3.5/UCA0RXD|<------------
;
;
; B. Nisarga
; Texas Instruments Inc.
; September 2007
; Built with IAR Embedded Workbench Version: 3.42A
;*******************************************************************************
#include "msp430x24x.h"
; CPU registers used
#define PointerTX R4
#define PointerRX R5
String1 EQU 0200h
;-------------------------------------------------------------------------------
RSEG CSTACK ; Define stack segment
;-------------------------------------------------------------------------------
RSEG CODE ; Assemble to Flash memory
;-------------------------------------------------------------------------------
RESET mov.w #SFE(CSTACK),SP ; Initialize stackpointer
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
SetupP1 mov.b #0FFh,&P1DIR ; All P1.x outputs
clr.b &P1OUT ; All P1.x reset
SetupP2 mov.b #0FFh,&P2DIR ; All P2.x outputs
clr.b &P2OUT ; All P2.x reset
SetupP3 bis.b #030h,&P3SEL ; P3.4,5 = USCI_A0 TXD/RXD
mov.b #0FFh,&P3DIR ; All P3.x outputs
clr.b &P3OUT ; All P3.x reset
SetupP4 mov.b #0FFh,&P4DIR ; All P4.x outputs
clr.b &P4OUT ; All P4.x reset
SetupUSCI0 bis.b #UCSSEL_1,&UCA0CTL1 ; CLK = ACLK
mov.b #03h,&UCA0BR0 ; 32kHz/9600 = 3.41
mov.b #00h,&UCA0BR1 ;
mov.b #UCBRS1+UCBRS0,&UCA0MCTL; Modulation UCBRSx = 3
bic.b #UCSWRST,&UCA0CTL1 ; **Initialize USCI state machine**
bis.b #UCA0RXIE,&IE2 ; Enable USCI_A0 RX interrupt
clr.w PointerRX ;
;
Mainloop bis.w #LPM3+GIE,SR ; Enter LPM3 w/ int until Byte RXed
nop ; Required only for debugger
;
;-------------------------------------------------------------------------------
USCI0TX_ISR;
;-------------------------------------------------------------------------------
mov.b @PointerTX+,&UCA0TXBUF ; TX next character
cmp.w #String1+8,PointerTX ; TX over?
jeq Done ;
reti ;
Done bic.b #UCA0TXIE,&IE2 ; Disable USCI_A0 TX interrupt
reti ;
;
;-------------------------------------------------------------------------------
USCI0RX_ISR;
;-------------------------------------------------------------------------------
mov.b &UCA0RXBUF,String1(PointerRX) ; Store RX data
inc.w PointerRX ;
cmp.b #8,PointerRX ;
jne UART_Done ;
bis.b #UCA0RXIE+UCA0TXIE,&IE2 ; Enable USCI_A0 TX interrupt
clr.w PointerRX ;
mov.w #String1,PointerTX ;
mov.b @PointerTX+,&UCA0TXBUF ;
UART_Done reti ;
;-------------------------------------------------------------------------------
COMMON INTVEC ; Interrupt Vectors
;-------------------------------------------------------------------------------
ORG USCIAB0RX_VECTOR
DW USCI0RX_ISR
ORG USCIAB0TX_VECTOR
DW USCI0TX_ISR
ORG RESET_VECTOR
DW RESET
END
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