?? msp430x24x_wdt_06.s43
字號:
;*******************************************************************************
; MSP430x24x Demo - WDT+ Failsafe Clock, 32kHz ACLK
;
; Description; Allow WDT+ in watchdog to timeout sourced by ACLK. LPM3 is
; entered, this example will demonstrate WDT+ feature by automatically
; re-enabling WDT+ clock source as DCO if external XTAL fails. This can be
; seen as a continued, though faster as clocked by DCO, watchdog timeout
; which will toggle on P1.0 in main function.
; ACLK = 32kHz, MCLK = SMCLK = default DCO ~1.045MHz
;
; MSP430F249
; -----------------
; /|\| XIN|-
; | | | 32kHz
; --|RST XOUT|-
; | |
; | P1.0|-->LED
;
; B. Nisarga
; Texas Instruments Inc.
; September 2007
; Built with IAR Embedded Workbench Version: 3.42A
;*******************************************************************************
#include "msp430x24x.h"
;-------------------------------------------------------------------------------
RSEG CSTACK ; Define stack segment
;-------------------------------------------------------------------------------
RSEG CODE ; Assemble to Flash memory
;-------------------------------------------------------------------------------
RESET mov.w #SFE(CSTACK),SP ; Initialize stackpointer
SetupWDT mov.w #WDT_ARST_1000,&WDTCTL ; Set Watchdog Timer timeout 1s
bis.b #001h,&P1DIR ; P1.0 output
xor.b #001h,&P1OUT ; Toggle P1.0
Mainloop bis.w #LPM3+GIE,SR ; Enter LPM3
nop ;
;-------------------------------------------------------------------------------
COMMON INTVEC ; Interrupt Vectors
;-------------------------------------------------------------------------------
ORG RESET_VECTOR ; MSP430 RESET Vector
DW RESET ;
END
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