?? csl_pcihal.h
字號:
#define _PCI_PCIIS_HOSTSW_SHIFT 0x00000003u #define PCI_PCIIS_HOSTSW_DEFAULT 0x00000000u #define PCI_PCIIS_HOSTSW_OF(x) _VALUEOF(x) #define PCI_PCIIS_HOSTSW_CLR 0x00000001u #define _PCI_PCIIS_PCIMASTER_MASK 0x00000004u #define _PCI_PCIIS_PCIMASTER_SHIFT 0x00000002u #define PCI_PCIIS_PCIMASTER_DEFAULT 0x00000000u #define PCI_PCIIS_PCIMASTER_OF(x) _VALUEOF(x) #define PCI_PCIIS_PCIMASTER_CLR 0x00000001u #define _PCI_PCIIS_PCITARGET_MASK 0x00000002u #define _PCI_PCIIS_PCITARGET_SHIFT 0x00000001u #define PCI_PCIIS_PCITARGET_DEFAULT 0x00000000u #define PCI_PCIIS_PCITARGET_OF(x) _VALUEOF(x) #define PCI_PCIIS_PCITARGET_CLR 0x00000001u #define _PCI_PCIIS_PWRMGMT_MASK 0x00000001u #define _PCI_PCIIS_PWRMGMT_SHIFT 0x00000000u #define PCI_PCIIS_PWRMGMT_DEFAULT 0x00000000u #define PCI_PCIIS_PWRMGMT_OF(x) _VALUEOF(x) #define PCI_PCIIS_PWRMGMT_CLR 0x00000001u #define PCI_PCIIS_OF(x) _VALUEOF(x) #define PCI_PCIIS_DEFAULT (Uint32)( \ _PER_FDEFAULT(PCI,PCIIS,DMAHALTED) \ |_PER_FDEFAULT(PCI,PCIIS,PRST) \ |_PER_FDEFAULT(PCI,PCIIS,EERDY) \ |_PER_FDEFAULT(PCI,PCIIS,CFGERR) \ |_PER_FDEFAULT(PCI,PCIIS,CFGDONE) \ |_PER_FDEFAULT(PCI,PCIIS,MASTEROK) \ |_PER_FDEFAULT(PCI,PCIIS,PWRHL) \ |_PER_FDEFAULT(PCI,PCIIS,PWRLH) \ |_PER_FDEFAULT(PCI,PCIIS,HOSTSW) \ |_PER_FDEFAULT(PCI,PCIIS,PCIMASTER) \ |_PER_FDEFAULT(PCI,PCIIS,PCITARGET) \ |_PER_FDEFAULT(PCI,PCIIS,PWRMGMT) \ ) #define PCI_PCIIS_RMK(dmahalted,prst,eerdy,cfgerr,cfgdone,masterok, \ pwrhl,pwrlh,hostsw,pcimaster,pcitarget,pwrmgmt)\ (Uint32)( \ _PER_FMK(PCI,PCIIS,DMAHALTED,dmahalted) \ |_PER_FMK(PCI,PCIIS,PRST,prst) \ |_PER_FMK(PCI,PCIIS,EERDY,eerdy) \ |_PER_FMK(PCI,PCIIS,CFGERR,cfgerr) \ |_PER_FMK(PCI,PCIIS,CFGDONE,cfgdone) \ |_PER_FMK(PCI,PCIIS,MASTEROK,masterok) \ |_PER_FMK(PCI,PCIIS,PWRHL,pwrhl) \ |_PER_FMK(PCI,PCIIS,PWRLH,pwrlh) \ |_PER_FMK(PCI,PCIIS,HOSTSW,hostsw) \ |_PER_FMK(PCI,PCIIS,PCIMASTER,pcimaster) \ |_PER_FMK(PCI,PCIIS,PCITARGET,pcitarget) \ |_PER_FMK(PCI,PCIIS,PWRMGMT,pwrmgmt) \ ) #define _PCI_PCIIS_FGET(FIELD)\ _PER_FGET(_PCI_PCIIS_ADDR,PCI,PCIIS,##FIELD) #define _PCI_PCIIS_FSET(FIELD,field)\ _PER_FSET(_PCI_PCIIS_ADDR,PCI,PCIIS,##FIELD,field) #define _PCI_PCIIS_FSETS(FIELD,SYM)\ _PER_FSETS(_PCI_PCIIS_ADDR,PCI,PCIIS,##FIELD,##SYM)/******************************************************************************\* _____________________* | |* | P C I I E N |* |___________________|** PCIIEN - PCI Interrupt Enable Register** FIELDS (msb -> lsb)* (rw) PRST* (rw) EERDY* (rw) CFGERR* (rw) CFGDONE* (rw) MASTEROK* (rw) PWRHL* (rw) PWRLH* (rw) HOSTSW* (rw) PCIMASTER* (rw) PCITARGET* (rw) PWRMGMT*\******************************************************************************/ #define _PCI_PCIIEN_OFFSET 3 #if (C64_SUPPORT) #define _PCI_PCIIEN_ADDR 0x01C0000Cu #else #define _PCI_PCIIEN_ADDR 0x01A4000Cu #endif #define _PCI_PCIIEN_PRST_MASK 0x00000800u #define _PCI_PCIIEN_PRST_SHIFT 0x0000000Bu #define PCI_PCIIEN_PRST_DEFAULT 0x00000000u #define PCI_PCIIEN_PRST_OF(x) _VALUEOF(x) #define PCI_PCIIEN_PRST_DISABLE 0x00000000u #define PCI_PCIIEN_PRST_ENABLE 0x00000001u #define _PCI_PCIIEN_EERDY_MASK 0x00000200u #define _PCI_PCIIEN_EERDY_SHIFT 0x00000009u #define PCI_PCIIEN_EERDY_DEFAULT 0x00000000u #define PCI_PCIIEN_EERDY_OF(x) _VALUEOF(x) #define PCI_PCIIEN_EERDY_DISABLE 0x00000000u #define PCI_PCIIEN_EERDY_ENABLE 0x00000001u #define _PCI_PCIIEN_CFGERR_MASK 0x00000100u #define _PCI_PCIIEN_CFGERR_SHIFT 0x00000008u #define PCI_PCIIEN_CFGERR_DEFAULT 0x00000000u #define PCI_PCIIEN_CFGERR_OF(x) _VALUEOF(x) #define PCI_PCIIEN_CFGERR_DISABLE 0x00000000u #define PCI_PCIIEN_CFGERR_ENABLE 0x00000001u #define _PCI_PCIIEN_CFGDONE_MASK 0x00000080u #define _PCI_PCIIEN_CFGDONE_SHIFT 0x00000007u #define PCI_PCIIEN_CFGDONE_DEFAULT 0x00000000u #define PCI_PCIIEN_CFGDONE_OF(x) _VALUEOF(x) #define PCI_PCIIEN_CFGDONE_DISABLE 0x00000000u #define PCI_PCIIEN_CFGDONE_ENABLE 0x00000001u #define _PCI_PCIIEN_MASTEROK_MASK 0x00000040u #define _PCI_PCIIEN_MASTEROK_SHIFT 0x00000006u #define PCI_PCIIEN_MASTEROK_DEFAULT 0x00000000u #define PCI_PCIIEN_MASTEROK_OF(x) _VALUEOF(x) #define PCI_PCIIEN_MASTEROK_DISABLE 0x00000000u #define PCI_PCIIEN_MASTEROK_ENABLE 0x00000001u #define _PCI_PCIIEN_PWRHL_MASK 0x00000020u #define _PCI_PCIIEN_PWRHL_SHIFT 0x00000005u #define PCI_PCIIEN_PWRHL_DEFAULT 0x00000000u #define PCI_PCIIEN_PWRHL_OF(x) _VALUEOF(x) #define PCI_PCIIEN_PWRHL_DISABLE 0x00000000u #define PCI_PCIIEN_PWRHL_ENABLE 0x00000001u #define _PCI_PCIIEN_PWRLH_MASK 0x00000010u #define _PCI_PCIIEN_PWRLH_SHIFT 0x00000004u #define PCI_PCIIEN_PWRLH_DEFAULT 0x00000000u #define PCI_PCIIEN_PWRLH_OF(x) _VALUEOF(x) #define PCI_PCIIEN_PWRLH_DISABLE 0x00000000u #define PCI_PCIIEN_PWRLH_ENABLE 0x00000001u #define _PCI_PCIIEN_HOSTSW_MASK 0x00000008u #define _PCI_PCIIEN_HOSTSW_SHIFT 0x00000003u #define PCI_PCIIEN_HOSTSW_DEFAULT 0x00000008u #define PCI_PCIIEN_HOSTSW_OF(x) _VALUEOF(x) #define PCI_PCIIEN_HOSTSW_DISABLE 0x00000000u #define PCI_PCIIEN_HOSTSW_ENABLE 0x00000001u #define _PCI_PCIIEN_PCIMASTER_MASK 0x00000004u #define _PCI_PCIIEN_PCIMASTER_SHIFT 0x00000002u #define PCI_PCIIEN_PCIMASTER_DEFAULT 0x00000000u #define PCI_PCIIEN_PCIMASTER_OF(x) _VALUEOF(x) #define PCI_PCIIEN_PCIMASTER_DISABLE 0x00000000u #define PCI_PCIIEN_PCIMASTER_ENABLE 0x00000001u #define _PCI_PCIIEN_PCITARGET_MASK 0x00000002u #define _PCI_PCIIEN_PCITARGET_SHIFT 0x00000001u #define PCI_PCIIEN_PCITARGET_DEFAULT 0x00000000u #define PCI_PCIIEN_PCITARGET_OF(x) _VALUEOF(x) #define PCI_PCIIEN_PCITARGET_DISABLE 0x00000000u #define PCI_PCIIEN_PCITARGET_ENABLE 0x00000001u #define _PCI_PCIIEN_PWRMGMT_MASK 0x00000001u #define _PCI_PCIIEN_PWRMGMT_SHIFT 0x00000000u #define PCI_PCIIEN_PWRMGMT_DEFAULT 0x00000000u #define PCI_PCIIEN_PWRMGMT_OF(x) _VALUEOF(x) #define PCI_PCIIEN_PWRMGMT_DISABLE 0x00000000u #define PCI_PCIIEN_PWRMGMT_ENABLE 0x00000001u #define PCI_PCIIEN_OF(x) _VALUEOF(x) #define PCI_PCIIEN_DEFAULT (Uint32)( \ _PER_FDEFAULT(PCI,PCIIEN,PRST) \ |_PER_FDEFAULT(PCI,PCIIEN,EERDY) \ |_PER_FDEFAULT(PCI,PCIIEN,CFGERR) \ |_PER_FDEFAULT(PCI,PCIIEN,CFGDONE) \ |_PER_FDEFAULT(PCI,PCIIEN,MASTEROK) \ |_PER_FDEFAULT(PCI,PCIIEN,PWRHL) \ |_PER_FDEFAULT(PCI,PCIIEN,PWRLH) \ |_PER_FDEFAULT(PCI,PCIIEN,HOSTSW) \ |_PER_FDEFAULT(PCI,PCIIEN,PCIMASTER) \ |_PER_FDEFAULT(PCI,PCIIEN,PCITARGET) \ |_PER_FDEFAULT(PCI,PCIIEN,PWRMGMT) \ ) #define PCI_PCIIEN_RMK(prst,eerdy,cfgerr,cfgdone,masterok, \ pwrhl,pwrlh,hostsw,pcimaster,pcitarget,pwrmgmt)\ (Uint32)( \ _PER_FMK(PCI,PCIIEN,PRST,prst) \ |_PER_FMK(PCI,PCIIEN,EERDY,eerdy) \ |_PER_FMK(PCI,PCIIEN,CFGERR,cfgerr) \ |_PER_FMK(PCI,PCIIEN,CFGDONE,cfgdone) \ |_PER_FMK(PCI,PCIIEN,MASTEROK,masterok) \ |_PER_FMK(PCI,PCIIEN,PWRHL,pwrhl) \ |_PER_FMK(PCI,PCIIEN,PWRLH,pwrlh) \ |_PER_FMK(PCI,PCIIEN,HOSTSW,hostsw) \ |_PER_FMK(PCI,PCIIEN,PCIMASTER,pcimaster) \ |_PER_FMK(PCI,PCIIEN,PCITARGET,pcitarget) \ |_PER_FMK(PCI,PCIIEN,PWRMGMT,pwrmgmt) \ ) #define _PCI_PCIIEN_FGET(FIELD)\ _PER_FGET(_PCI_PCIIEN_ADDR,PCI,PCIIEN,##FIELD) #define _PCI_PCIIEN_FSET(FIELD,field)\ _PER_FSET(_PCI_PCIIEN_ADDR,PCI,PCIIEN,##FIELD,field) #define _PCI_PCIIEN_FSETS(FIELD,SYM)\ _PER_FSETS(_PCI_PCIIEN_ADDR,PCI,PCIIEN,##FIELD,##SYM)/******************************************************************************\* _____________________* | |* | D S P M A |* |___________________|** DSPMA - DSP Master Address Register** FIELDS (msb -> lsb)* (rw) ADDRMA* (rw) AINC*\******************************************************************************/ #define _PCI_DSPMA_OFFSET 4 #if (C64_SUPPORT) #define _PCI_DSPMA_ADDR 0x01C00010u #else #define _PCI_DSPMA_ADDR 0x01A40010u #endif #define _PCI_DSPMA_ADDRMA_MASK 0xFFFFFFFCu #define _PCI_DSPMA_ADDRMA_SHIFT 0x00000002u #define PCI_DSPMA_ADDRMA_DEFAULT 0x00000000u #define PCI_DSPMA_ADDRMA_OF(x) _VALUEOF(x) #define _PCI_DSPMA_AINC_MASK 0x00000002u #define _PCI_DSPMA_AINC_SHIFT 0x00000001u #define PCI_DSPMA_AINC_DEFAULT 0x00000000u #define PCI_DSPMA_AINC_OF(x) _VALUEOF(x) #define PCI_DSPMA_AINC_ENABLE 0x00000000u #define PCI_DSPMA_AINC_DISABLE 0x00000001u #define PCI_DSPMA_OF(x) _VALUEOF(x) #define PCI_DSPMA_DEFAULT (Uint32)( \ _PER_FDEFAULT(PCI,DSPMA,ADDRMA) \ |_PER_FDEFAULT(PCI,DSPMA,AINC) \ ) #define PCI_DSPMA_RMK(addrma,ainc)\ (Uint32)( \ _PER_FMK(PCI,DSPMA,ADDRMA,addrma) \ |_PER_FMK(PCI,DSPMA,AINC,ainc) \ ) #define _PCI_DSPMA_FGET(FIELD)\ _PER_FGET(_PCI_DSPMA_ADDR,PCI,DSPMA,##FIELD) #define _PCI_DSPMA_FSET(FIELD,field)\ _PER_FSET(_PCI_DSPMA_ADDR,PCI,DSPMA,##FIELD,field) #define _PCI_DSPMA_FSETS(FIELD,SYM)\ _PER_FSETS(_PCI_DSPMA_ADDR,PCI,DSPMA,##FIELD,##SYM)/******************************************************************************\* _____________________* | |* | P C I M A |* |___________________|** PCIMA - PCI Master Address Register** FIELDS (msb -> lsb)* (rw) ADDRMA*\******************************************************************************/ #define _PCI_PCIMA_OFFSET 5 #if (C64_SUPPORT) #define _PCI_PCIMA_ADDR 0x01C00014u #else #define _PCI_PCIMA_ADDR 0x01A40014u #endif #define _PCI_PCIMA_ADDRMA_MASK 0xFFFFFFFCu #define _PCI_PCIMA_ADDRMA_SHIFT 0x00000002u #define PCI_PCIMA_ADDRMA_DEFAULT 0x00000000u #define PCI_PCIMA_ADDRMA_OF(x) _VALUEOF(x) #define PCI_PCIMA_OF(x) _VALUEOF(x) #define PCI_PCIMA_DEFAULT (Uint32)( \ _PER_FDEFAULT(PCI,PCIMA,ADDRMA) \ ) #define PCI_PCIMA_RMK(addrma)\ (Uint32)( \ _PER_FMK(PCI,PCIMA,ADDRMA,addrma) \ ) #define _PCI_PCIMA_FGET(FIELD)\ _PER_FGET(_PCI_PCIMA_ADDR,PCI,PCIMA,##FIELD) #define _PCI_PCIMA_FSET(FIELD,field)\ _PER_FSET(_PCI_PCIMA_ADDR,PCI,PCIMA,##FIELD,field) #define _PCI_PCIMA_FSETS(FIELD,SYM)\ _PER_FSETS(_PCI_PCIMA_ADDR,PCI,PCIMA,##FIELD,##SYM)/******************************************************************************\* _____________________* | |* | P C I M C |* |___________________|** PCIMC - PCI Master Control Register** FIELDS (msb -> lsb)* (rw) CNT* (rw) START*\******************************************************************************/ #define _PCI_PCIMC_OFFSET 6 #if (C64_SUPPORT) #define _PCI_PCIMC_ADDR 0x01C00018u #else #define _PCI_PCIMC_ADDR 0x01A40018u #endif #define _PCI_PCIMC_CNT_MASK 0xFFFF0000u #define _PCI_PCIMC_CNT_SHIFT 0x00000010u #define PCI_PCIMC_CNT_DEFAULT 0x00000000u #define PCI_PCIMC_CNT_OF(x) _VALUEOF(x) #define _PCI_PCIMC_START_MASK 0x00000007u #define _PCI_PCIMC_START_SHIFT 0x00000000u #define PCI_PCIMC_START_DEFAULT 0x00000000u #define PCI_PCIMC_START_OF(x) _VALUEOF(x) #define PCI_PCIMC_START_FLUSH 0x00000000u #define PCI_PCIMC_START_WRITE 0x00000001u #define PCI_PCIMC_START_READPREF 0x00000002u #define PCI_PCIMC_START_READNOPREF 0x00000003u #define PCI_PCIMC_START_CONFIGWRITE 0x00000004u #define PCI_PCIMC_START_CONFIGREAD 0x00000005u #define PCI_PCIMC_START_IOWRITE 0x00000006u #define PCI_PCIMC_START_IOREAD 0x00000007u #define PCI_PCIMC_OF(x) _VALUEOF(x) #define PCI_PCIMC_DEFAULT (Uint32)( \ _PER_FDEFAULT(PCI,PCIMC,CNT) \ |_PER_FDEFAULT(PCI,PCIMC,START) \ ) #define PCI_PCIMC_RMK(cnt,start)\ (Uint32)( \ _PER_FMK(PCI,PCIMC,CNT,cnt) \ |_PER_FMK(PCI,PCIMC,START,start) \ ) #define _PCI_PCIMC_FGET(FIELD)\ _PER_FGET(_PCI_PCIMC_ADDR,PCI,PCIMC,##FIELD) #define _PCI_PCIMC_FSET(FIELD,field)\ _PER_FSET(_PCI_PCIMC_ADDR,PCI,PCIMC,##FIELD,field) #define _PCI_PCIMC_FSETS(FIELD,SYM)\ _PER_FSETS(_PCI_PCIMC_ADDR,PCI,PCIMC,##FIELD,##SYM)/******************************************************************************\* _____________________* | |* | C D S P A |* |___________________|** CDSPA - Current DSP Address Register** FIELDS (msb -> lsb)* (r) CDSPA*\******************************************************************************/ #define _PCI_CDSPA_OFFSET 7 #if (C64_SUPPORT) #define _PCI_CDSPA_ADDR 0x01C0001Cu #else #define _PCI_CDSPA_ADDR 0x01A4001Cu #endif #define _PCI_CDSPA_CDSPA_MASK 0xFFFFFFFFu #define _PCI_CDSPA_CDSPA_SHIFT 0x00000000u #define PCI_CDSPA_CDSPA_DEFAULT 0x00000000u #define PCI_CDSPA_CDSPA_OF(x) _VALUEOF(x)?? 快捷鍵說明
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