/**************************************************************************** * QLogic qla2x00 device driver for Linux 2.2.x (redhat 6.X). * Copyright (C) 2000 Qlogic Corporation  * (www.qlogic.com) * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2, or (at your option) any * later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU * General Public License for more details. ****************************************************************************/#ifndef _IO_HBA_QLA2100_H          /* wrapper symbol for kernel use */#define _IO_HBA_QLA2100_H          /* subject to change without notice */#ifndef LINUX_VERSION_CODE #include <linux/version.h>#endif  /* LINUX_VERSION_CODE not defined */#if defined(__cplusplus)extern "C" {#endif#ifndef ISP2200 #define ISP2200#endif/* * Driver debug definitions. *//* #define QL_DEBUG_LEVEL_1 */      /* Output register accesses to COM2. *//* #define QL_DEBUG_LEVEL_2 */         /* Output error msgs to COM2. *//* #define QL_DEBUG_LEVEL_3 */       /* Output function trace msgs to COM2. *//* #define QL_DEBUG_LEVEL_4 */      /* Output NVRAM trace msgs to COM2. *//* #define QL_DEBUG_LEVEL_5 */      /* Output ring trace msgs to COM2. *//* #define QL_DEBUG_LEVEL_6 */      /* Output WATCHDOG timer trace to COM2. *//* #define QL_DEBUG_LEVEL_7 */      /* Output RISC load trace msgs to COM2. *//* #define QL_DEBUG_LEVEL_8 */      /* Output ring saturation msgs to COM2. */#define QL_DEBUG_CONSOLE              /* Output to console instead of COM2. *//* * Data bit definitions. */#define BIT_0   0x1#define BIT_1   0x2#define BIT_2   0x4#define BIT_3   0x8#define BIT_4   0x10#define BIT_5   0x20#define BIT_6   0x40#define BIT_7   0x80#define BIT_8   0x100#define BIT_9   0x200#define BIT_10  0x400#define BIT_11  0x800#define BIT_12  0x1000#define BIT_13  0x2000#define BIT_14  0x4000#define BIT_15  0x8000#define BIT_16  0x10000#define BIT_17  0x20000#define BIT_18  0x40000#define BIT_19  0x80000#define BIT_20  0x100000#define BIT_21  0x200000#define BIT_22  0x400000#define BIT_23  0x800000#define BIT_24  0x1000000#define BIT_25  0x2000000#define BIT_26  0x4000000#define BIT_27  0x8000000#define BIT_28  0x10000000#define BIT_29  0x20000000#define BIT_30  0x40000000#define BIT_31  0x80000000/* * Common size type definitions */#if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0)typedef unsigned char  uint8_t; typedef unsigned short uint16_t; typedef unsigned long  uint32_t; typedef char  int8_t; typedef short int16_t; typedef long  int32_t; #endif/* *  Local Macro Definitions. */#if defined(QL_DEBUG_LEVEL_1) || defined(QL_DEBUG_LEVEL_2) || \    defined(QL_DEBUG_LEVEL_3) || defined(QL_DEBUG_LEVEL_4) || \    defined(QL_DEBUG_LEVEL_5) || defined(QL_DEBUG_LEVEL_6) || \    defined(QL_DEBUG_LEVEL_7) || defined(QL_DEBUG_LEVEL_8)    #define QL_DEBUG_ROUTINES#endif#ifndef TRUE    #define TRUE  1#endif#ifndef FALSE    #define FALSE 0#endif#ifndef KERNEL_VERSION#  define KERNEL_VERSION(x,y,z) (((x)<<16)+((y)<<8)+(z))#endif#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,1,92)#  if defined(__sparc_v9__) || defined(__powerpc__)#    error "PPC and Sparc platforms are only support under 2.1.92 and above"#  endif#endif/*  * Locking */#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0)#  include <asm/spinlock.h>#  include <linux/smp.h>#  define cpuid smp_processor_id()#  if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)#    define DRIVER_LOCK_INIT \       spin_lock_init(&ha->spin_lock);#    define DRIVER_LOCK \       if(!ha->cpu_lock_count[cpuid]) { \         spin_lock_irqsave(&ha->spin_lock, cpu_flags); \         ha->cpu_lock_count[cpuid]++; \       } else { \         ha->cpu_lock_count[cpuid]++; \       }#    define DRIVER_UNLOCK \       if(--ha->cpu_lock_count[cpuid] == 0) \         spin_unlock_irqrestore(&ha->spin_lock, cpu_flags);#  else#    define DRIVER_LOCK_INIT#    define DRIVER_LOCK#    define DRIVER_UNLOCK#  endif #else#  define cpuid 0#  define DRIVER_LOCK_INIT#  define DRIVER_LOCK \       save_flags(cpu_flags); \       cli();#  define DRIVER_UNLOCK \       restore_flags(cpu_flags);#  define le32_to_cpu(x) (x)#  define cpu_to_le32(x) (x)#endif/* * I/O register*//* #define MEMORY_MAPPED_IO  */           /* Enable memory mapped I/O */#undef MEMORY_MAPPED_IO            /* Disable memory mapped I/O */#define LINUX_IOPORTS                     /* Linux in/out routines are define*/                                          /* differently from other OSs      */#ifdef QL_DEBUG_LEVEL_1    #define RD_REG_BYTE(addr)         qla2100_getbyte((uint8_t *)addr)    #define RD_REG_WORD(addr)         qla2100_getword((uint16_t *)addr)    #define RD_REG_DWORD(addr)        qla2100_getdword((uint32_t *)addr)    #define WRT_REG_BYTE(addr, data)  qla2100_putbyte((uint8_t *)addr, data)    #define WRT_REG_WORD(addr, data)  qla2100_putword((uint16_t *)addr, data)    #define WRT_REG_DWORD(addr, data) qla2100_putdword((uint32_t *)addr, data)#else  /* QL_DEBUG_LEVEL_1 */#ifdef MEMORY_MAPPED_IO#define RD_REG_BYTE(addr)         (*((volatile uint8_t *)addr))#define RD_REG_WORD(addr)         (*((volatile uint16_t *)addr))#define RD_REG_DWORD(addr)        (*((volatile uint32_t *)addr))#define WRT_REG_BYTE(addr, data)  (*((volatile uint8_t *)addr) = data)#define WRT_REG_WORD(addr, data)  (*((volatile uint16_t *)addr) = data)#define WRT_REG_DWORD(addr, data) (*((volatile uint32_t *)addr) = data)#else   /* MEMORY_MAPPED_IO */#define RD_REG_BYTE(addr)         (inb((int)addr))#define RD_REG_WORD(addr)         (inw((int)addr))#define RD_REG_DWORD(addr)        (inl((int)addr))#define WRT_REG_BYTE(addr, data)  (outb(data,(int)addr))#define WRT_REG_WORD(addr, data)  (outw(data,(int)addr))#define WRT_REG_DWORD(addr, data) (outl(data,(int)addr))#endif  /* MEMORY_MAPPED_IO */#endif    /* QL_DEBUG_LEVEL_1 */#define MAX_FIBRE_DEVICES   256#define	MAX_RSCN_COUNT		10#define	MAX_HOST_COUNT		8/* * Host adapter default definitions. */#define MAX_BUSES       1               /* indicates 1 SCSI bus */#define MAX_TARGETS_2100     255        /* (+1) number of targets on bus */#define MAX_TARGETS_2200     255        /* (+1) number of targets on bus */#define MAX_LUNS        255             /* (+1) number of luns on bus */                                    /* * Fibre Channel device definitions. */#define LAST_LOCAL_LOOP_ID  0x7d#define SNS_FL_PORT         0x7e#define FABRIC_CONTROLLER   0x7f#define SIMPLE_NAME_SERVER  0x80#define SNS_FIRST_LOOP_ID   0x81#define LAST_SNS_LOOP_ID    0xfe#define BROADCAST           0xff#define SNS_ACCEPT          0x0280      /* 8002 swapped */#define SNS_REJECT          0x0180      /* 8001 swapped *//* Loop ID's used as database flags, must be higher than any valid Loop ID */#define PORT_UNUSED         0x100       /* Port never been used. */#define PORT_AVAILABLE      0x101       /* Device does not exist on port. *//* * Timeout timer counts in seconds */#define QLA2100_WDG_TIME_QUANTUM   1    /* In seconds */#define PORT_RETRY_TIME            2#define LOOP_DOWN_TIMEOUT          60#define LOOP_DOWN_TIME             240      /* 240 */#define	LOOP_DOWN_RESET		(LOOP_DOWN_TIME - 30)/* Maximum outstanding commands in ISP queues (1-65535) */#define MAX_OUTSTANDING_COMMANDS   512*2/* ISP request and response entry counts (37-65535) */#if 0#define REQUEST_ENTRY_CNT       256     /* Number of request entries. */#define RESPONSE_ENTRY_CNT      16      /* Number of response entries. */#endif#define REQUEST_ENTRY_CNT       512     /* Number of request entries. */#define RESPONSE_ENTRY_CNT      64      /* Number of response entries. *//* * UnixWare required definitions. */#define HBA_PREFIX qla2100/* Physical DMA memory requirements */#define QLA2100_MEMALIGN    4#define QLA2100_BOUNDARY    0x80000000  /* 2GB *//* Number of segments 1 - 65535 */#define SG_SEGMENTS     32             /* Cmd entry + 6 continuations */typedef struct timer_list   timer_t;         /* timer *//* * SCSI Request Block  */typedef struct srb{    Scsi_Cmnd  *cmd;                 /* (4) SCSI command block */    struct srb  *s_next;             /* (4) Next block on LU queue */    struct srb  *s_prev;             /* (4) Previous block on LU queue */    uint8_t     flags;               /* (1) Status flags. */    uint8_t     dir;                 /* direction of transfer */    uint8_t     retry_count;            /* Retry count. */    uint8_t     port_down_retry_count;  /* Port down retry count. */    u_long      r_start;             /* jiffies at start of request */    u_long      u_start;             /* jiffies when sent to F/W    */    uint8_t     ccode;               /* risc completion code */    uint8_t     wdg_time;            /* watchdog time in seconds */    uint8_t     state;               /* Q state code */}srb_t;/* * SRB flag definitions */#define SRB_TIMEOUT     BIT_0           /* Command timed out */#define SRB_SENT        BIT_1           /* Command sent to ISP */#define SRB_WATCHDOG    BIT_2           /* Command on watchdog list */#define SRB_ABORT_PENDING BIT_3     /* Command abort sent to device */#define SRB_ABORTED     BIT_4           /* Command aborted command already */#define SRB_RETRY     BIT_5           /* Command aborted command already *//* * LUN - Logical Unit Queue structure */typedef struct scsi_lu{    srb_t           *q_first;           /* First block on LU queue */    srb_t           *q_last;            /* Last block on LU queue */    u_char          q_flag;             /* LU queue state flags */    u_short         q_outcnt;           /* Pending jobs for this LU */    u_long          q_incnt;            /* queued jobs for this LU */    u_long          io_cnt;             /* total xfer count */    u_long          resp_time;          /* total response time (start - finish) */    u_long          act_time;           /* total actived time (minus queuing time) */    u_long          w_cnt;              /* total writes */    u_long          r_cnt;              /* total reads */#if QLA2X00_TARGET_MODE_SUPPORT    void            (*q_func)();        /* Target driver event handler */    long            q_param;            /* Target driver event param */#endif#if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0)    spinlock_t      *q_spin_lock;       /* Device Queue Lock */#endif    volatile unsigned char cpu_lock_count[NR_CPUS];    u_long          q_timeout;           /* total command timeouts */}scsi_lu_t;/* * Logical Unit q_flag definitions */#define QLA2100_QBUSY   BIT_0#define QLA2100_QWAIT   BIT_1#define QLA2100_QSUSP   BIT_2#define QLA2100_QRESET  BIT_4#define QLA2100_QHBA    BIT_5#define QLA2100_BSUSP   BIT_6           /* controller is suspended */#define QLA2100_BREM    BIT_7           /* controller is removed *//* *  ISP PCI Configuration Register Set */typedef volatile struct{    uint16_t vendor_id;                 /* 0x0 */    uint16_t device_id;                 /* 0x2 */    uint16_t command;                   /* 0x4 */    uint16_t status;                    /* 0x6 */    uint8_t revision_id;                /* 0x8 */    uint8_t programming_interface;      /* 0x9 */    uint8_t sub_class;                  /* 0xa */    uint8_t base_class;                 /* 0xb */    uint8_t cache_line;                 /* 0xc */    uint8_t latency_timer;              /* 0xd */    uint8_t header_type;                /* 0xe */    uint8_t bist;                       /* 0xf */    uint32_t base_port;                 /* 0x10 */    uint32_t mem_base_addr;             /* 0x14 */    uint32_t base_addr[4];              /* 0x18-0x24 */    uint32_t reserved_1[2];             /* 0x28-0x2c */    uint16_t expansion_rom;             /* 0x30 */    uint32_t reserved_2[2];             /* 0x34-0x38 */    uint8_t interrupt_line;             /* 0x3c */    uint8_t interrupt_pin;              /* 0x3d */    uint8_t min_grant;                  /* 0x3e */    uint8_t max_latency;                /* 0x3f */}config_reg_t;/* *  ISP I/O Register Set structure definitions. */typedef volatile struct{    uint16_t flash_address;             /* Flash BIOS address */    uint16_t flash_data;                /* Flash BIOS data */    uint16_t unused_1[1];               /* Gap */    uint16_t ctrl_status;               /* Control/Status */        #define ISP_FLASH_ENABLE BIT_1  /* Flash BIOS Read/Write enable */        #define ISP_RESET       BIT_0   /* ISP soft reset */    uint16_t ictrl;                     /* Interrupt control */        #define ISP_EN_INT      BIT_15  /* ISP enable interrupts. */        #define ISP_EN_RISC     BIT_3   /* ISP enable RISC interrupts. */    uint16_t istatus;                   /* Interrupt status */        #define RISC_INT        BIT_3   /* RISC interrupt */    uint16_t semaphore;                 /* Semaphore */    uint16_t nvram;                     /* NVRAM register. */        #define NV_DESELECT     0        #define NV_CLOCK        BIT_0        #define NV_SELECT       BIT_1        #define NV_DATA_OUT     BIT_2        #define NV_DATA_IN      BIT_3    uint16_t mailbox0;                  /* Mailbox 0 */    uint16_t mailbox1;                  /* Mailbox 1 */    uint16_t mailbox2;                  /* Mailbox 2 */    uint16_t mailbox3;                  /* Mailbox 3 */    uint16_t mailbox4;                  /* Mailbox 4 */    uint16_t mailbox5;                  /* Mailbox 5 */    uint16_t mailbox6;                  /* Mailbox 6 */    uint16_t mailbox7;                  /* Mailbox 7 */#if 0    uint16_t unused_2[0x50];            /* Gap */#else	uint16_t unused_2[0x3b];	/* Gap */	uint16_t fpm_diag_config;