#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) /* (PIOA) Multi-driver Enable Register */#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) /* (PIOA) PIO Enable Register */#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) /* (PIOA) PIO Status Register */#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) /* (PIOA) Output Enable Register */#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) /* (PIOA) Select B Register */#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) /* (PIOA) Pull-up Enable Register */#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) /* (PIOA) Multi-driver Disable Register */#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) /* (PIOA) PIO Disable Register */#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) /* (PIOA) Output Disable Register */#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) /* (PIOA) Input Filter Disable Register */#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) /* (PIOA) AB Select Status Register */#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) /* (PIOA) Select A Register */#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) /* (PIOA) Pad Pull-up Status Register */#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) /* (PIOA) Output Data Status Register */#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) /* (PIOA) Set Output Data Register */#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) /* (PIOA) Input Filter Status Register */#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) /* (PIOA) Input Filter Enable Register */#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) /* (PIOA) Output Status Register */#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) /* (PIOA) Interrupt Disable Register */#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) /* (PIOA) Pin Data Status Register */#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) /* (PIOA) Clear Output Data Register */#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) /* (PIOA) Output Write Status Register */#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) /* (PIOA) Output Write Enable Register */#endif/* PIO interrupt level */#define AT91C_INT_LVL_PIOA			2 /*parallel I/O controller A */#define AT91C_INT_LVL_PIOB			3 /*parallel I/O controller B */#define AT91C_INT_LVL_PIOC			4 /*parallel I/O controller C */#define AT91C_INT_LVL_PIOD			5 /*parallel I/O controller D */#ifndef KBD_MSE_INT_LVL#define KBD_MSE_INT_LVL           AT91C_INT_LVL_PIOB#endif #ifndef KBD_MSE_INT_VEC#define KBD_MSE_INT_VEC           INUM_TO_IVEC(AT91C_INT_LVL_PIOB)#endif #define AT91C_AIC_SMR0   ((AT91_REG *) 	0xFFFFF000) /* (AIC) Source Mode Register */#define AT91C_AIC_SMR1   ((AT91_REG *) 	0xFFFFF004) /* (AIC) Source Mode Register */#define AT91C_AIC_SMR2   ((AT91_REG *) 	0xFFFFF008) /* (AIC) Source Mode Register */#define AT91C_AIC_SMR3   ((AT91_REG *) 	0xFFFFF00C) /* (AIC) Source Mode Register */#define AT91C_AIC_SMR4   ((AT91_REG *) 	0xFFFFF010) /* (AIC) Source Mode Register */#define AT91C_AIC_SMR5   ((AT91_REG *) 	0xFFFFF014) /* (AIC) Source Mode Register *//* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) /* (AIC) Priority Level */#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) /* (AIC) Lowest priority level */#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) /* (AIC) Highest priority level */#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) /* (AIC) Interrupt Source Type */#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  ((unsigned int) 0x0 <<  5) /* (AIC) Internal Sources Code Label Level Sensitive */#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   ((unsigned int) 0x1 <<  5) /* (AIC) Internal Sources Code Label Edge triggered */#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       ((unsigned int) 0x2 <<  5) /* (AIC) External Sources Code Label High-level Sensitive */#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    ((unsigned int) 0x3 <<  5) /* (AIC) External Sources Code Label Positive Edge triggered *//*mouse defination*/#define MSE_CLK		0x400		/*pb8 --10*/#define MSE_DATA	0x200		/*pb7 --9*/#define	MSE_CLK_OUTPUT			(*AT91C_PIOB_OER = MSE_CLK)#define MSE_CLK_INPUT			(*AT91C_PIOB_ODR = MSE_CLK)#define	MSE_DATA_OUTPUT			(*AT91C_PIOB_OER = MSE_DATA)#define MSE_DATA_INPUT			(*AT91C_PIOB_ODR = MSE_DATA)#define MSE_INT_ENABLE			(*AT91C_PIOB_IER = MSE_CLK)#define MSE_INT_DISABLE			(*AT91C_PIOB_IDR = MSE_CLK)#define MSE_CLK_WRITE(clk) 		((clk?(*AT91C_PIOB_SODR):(*AT91C_PIOB_CODR)) = MSE_CLK)		#define MSE_DATA_WRITE(data)	((data?(*AT91C_PIOB_SODR):(*AT91C_PIOB_CODR)) = MSE_DATA)	#define	MSE_CLK_READ			((*AT91C_PIOB_PDSR & MSE_CLK)>>10)/*define	MSE_CLK_READ			(*AT91C_PIOB_PDSR & MSE_CLK)	*/#define MSE_DATA_READ			((*AT91C_PIOB_PDSR & MSE_DATA)>>9)	/*keyboard defination*/#define KBD_CLK		0x100		/*pb8 */#define KBD_DATA	0x80		/*pb7 */#define	KBD_CLK_READ			((*AT91C_PIOB_PDSR & KBD_CLK)>>8)/*#define	KBD_CLK_READ			(*AT91C_PIOB_PDSR & KBD_CLK) */#define KBD_DATA_READ			((*AT91C_PIOB_PDSR & KBD_DATA)>>7)	#define	KBD_CLK_OUTPUT			(*AT91C_PIOB_OER = KBD_CLK)#define KBD_CLK_INPUT			(*AT91C_PIOB_ODR = KBD_CLK)#define	KBD_DATA_OUTPUT			(*AT91C_PIOB_OER = KBD_DATA)#define KBD_DATA_INPUT			(*AT91C_PIOB_ODR = KBD_DATA)#define KBD_INT_ENABLE			(*AT91C_PIOB_IER = KBD_CLK)#define KBD_INT_DISABLE			(*AT91C_PIOB_IDR = KBD_CLK)#define KBD_CLK_WRITE(clk) 		((clk?(*AT91C_PIOB_SODR):(*AT91C_PIOB_CODR)) = KBD_CLK)		#define KBD_DATA_WRITE(data)	((data?(*AT91C_PIOB_SODR):(*AT91C_PIOB_CODR)) = KBD_DATA)	/* typedefs */typedef struct    {    TY_DEV          ty_dev;    } MSE_DEVICE;/* pc console device descriptor */typedef struct    {    TY_DEV  tyDev;    UINT16  kbdFlags;       /* 16 bit keyboard flags */    } KBD_DEVICE;extern STATUS at91cKbdDevCreate(char *  name);/*extern STATUS at91cKBWrite(unsigned char data);*//*extern at91ckbdIntr(void);*/extern STATUS at91cPs2DevCreate(char *  name);/*extern STATUS at91cMsWrite (unsigned char data);extern STATUS ambaMsRead (unsigned char *data);extern STATUS ambaMsCommand (unsigned char data);*/#if __cplusplus} /* extern "C" */#endif#endif /* __INCambakmih */