?? second.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
entity second is
port(a,b,c,zin,yin:in std_logic;
dout,eout,fout,gout:out std_logic);
end second;
architecture rtl of second is
begin
process(a,zin,yin)
begin
if(a='1')then
dout<='1';
eout<=zin;
else
dout<='0';
eout<=yin;
end if;
end process;
process(a,b)
begin
if(b='1')then
fout<='1';
else
fout<='0';
end if;
end process;
process(c,a,b)
begin
if(b='1' and a='1' and c='1')then
gout<='1';
else
gout<='0';
end if;
end process;
end rtl;
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