#define CLKXP         0x0002
#define DX_STAT       0x0020

#define SPCR10_VAL     0x0000
#define SPCR20_VAL     0x0200
//2 words per frame
#define RCR10_VAL      0x0140
#define RCR20_VAL      0x04
//2 words per frame
#define XCR10_VAL      0x0140
#define XCR20_VAL      0x04
#define PCR0_VAL       0x01


//MCBSP1:
//CLKG=16.9344*6M/48=2.1168M,幀脈沖寬度=24
#define SRGR1_VAL1      (15<<8)+249
//#define SRGR1_VAL1      (23<<8)+47

//幀長度=48、CLK由CPU的時鐘驅動、由FSG驅動
//#define SRGR2_VAL1      0x3000+47
#define SRGR2_VAL1      0x3000+31

//發送幀同步、時鐘由內部產生（11 9位=1)
//接收幀同步、時鐘由外部產生（10 8位=0)
//幀同步高有效，（2 3位=0），  下降沿有效（2 3位=1）
//時鐘上升沿有效（最后2位=0），下降沿有效（最后2位=1）
//send引腳配置成IO，
//CLKXM=1->OUT
#define PCR_VAL1       0x2a03
//引腳配置成串口
//#define PCR_VAL1       0x0a03

//DX is on(7=True) 
//RINT by RRDY
#define SPCR1_VAL1     0x0080

// 一幀2個字，每字24bit  vcd
//#define XCR1_VAL1      0x0180
#define XCR1_VAL1      0x0140
// 單相幀、無壓縮、0-bit延遲
#define XCR2_VAL1      0x0004

// 一幀2個字，每字24bit vcd
//#define RCR1_VAL1      0x0180
#define RCR1_VAL1      0x0140
// 單相幀、無壓縮、0-bit延遲
#define RCR2_VAL1      0x0004


//McBSP Memory Mapped Registers
#define CLKMD         (unsigned int *)0x58
#define SWCR          (unsigned int *)0x2b
#define IMR           (unsigned int *)0x00

#define SPSA0         (unsigned int *)0x38
#define SPSD0         (unsigned int *)0x39
#define DRR20         (unsigned int *)0x20
#define DRR10         (unsigned int *)0x21
#define DXR20         (unsigned int *)0x22
#define DXR10         (unsigned int *)0x23

#define SPSA1         (unsigned int *)0x48
#define SPSD1         (unsigned int *)0x49
#define DRR21         (unsigned int *)0x40
#define DRR11         (unsigned int *)0x41
#define DXR21         (unsigned int *)0x42
#define DXR11         (unsigned int *)0x43

// McBSP Subaddresed Registers
#define SPCR1          0x00
#define SPCR2          0x01
#define RCR1           0x02
#define RCR2           0x03
#define XCR1           0x04
#define XCR2           0x05
#define SRGR1          0x06
#define SRGR2          0x07
#define PCR            0x0E