dump_resmap();#endif}/********************************************************************          CCIO dma_ops support routines*******************************************************************/typedef unsigned long space_t;#define KERNEL_SPACE 0/*** DMA "Page Type" and Hints ** o if SAFE_DMA isn't set, mapping is for FAST_DMA. SAFE_DMA should be**   set for subcacheline DMA transfers since we don't want to damage the**   other part of a cacheline.** o SAFE_DMA must be set for "memory" allocated via pci_alloc_consistent().**   This bit tells U2 to do R/M/W for partial cachelines. "Streaming"**   data can avoid this if the mapping covers full cache lines.** o STOP_MOST is needed for atomicity across cachelines.**   Apperently only "some EISA devices" need this.**   Using CONFIG_ISA is hack. Only the IOA with EISA under it needs**   to use this hint iff the EISA devices needs this feature.**   According to the U2 ERS, STOP_MOST enabled pages hurt performance.** o PREFETCH should *not* be set for cases like Multiple PCI devices**   behind GSCtoPCI (dino) bus converter. Only one cacheline per GSC**   device can be fetched and multiply DMA streams will thrash the**   prefetch buffer and burn memory bandwidth. See 6.7.3 "Prefetch Rules**   and Invalidation of Prefetch Entries".**** FIXME: the default hints need to be per GSC device - not global.** ** HP-UX dorks: linux device driver programming model is totally different**    than HP-UX's. HP-UX always sets HINT_PREFETCH since it's drivers**    do special things to work on non-coherent platforms...linux has to**    be much more careful with this.*/#define IOPDIR_VALID    0x01UL#define HINT_SAFE_DMA   0x02UL	/* used for pci_alloc_consistent() pages */#ifdef CONFIG_ISA	/* EISA support really */#define HINT_STOP_MOST  0x04UL	/* LSL support */#else#define HINT_STOP_MOST  0x00UL	/* only needed for "some EISA devices" */#endif#define HINT_UDPATE_ENB 0x08UL  /* not used/supported by U2 */#define HINT_PREFETCH   0x10UL	/* for outbound pages which are not SAFE *//*** Use direction (ie PCI_DMA_TODEVICE) to pick hint.** ccio_alloc_consistent() depends on this to get SAFE_DMA** when it passes in BIDIRECTIONAL flag.*/static u32 hint_lookup[] = {	[PCI_DMA_BIDIRECTIONAL]  HINT_STOP_MOST | HINT_SAFE_DMA | IOPDIR_VALID,	[PCI_DMA_TODEVICE]       HINT_STOP_MOST | HINT_PREFETCH | IOPDIR_VALID,	[PCI_DMA_FROMDEVICE]     HINT_STOP_MOST | IOPDIR_VALID,	[PCI_DMA_NONE]           0,            /* not valid */};/*** Initialize an I/O Pdir entry**** Given a virtual address (vba, arg2) and space id, (sid, arg1),** load the I/O PDIR entry pointed to by pdir_ptr (arg0). Each IO Pdir** entry consists of 8 bytes as shown below (MSB == bit 0):****** WORD 0:** +------+----------------+-----------------------------------------------+** | Phys | Virtual Index  |               Phys                            |** | 0:3  |     0:11       |               4:19                            |** |4 bits|   12 bits      |              16 bits                          |** +------+----------------+-----------------------------------------------+** WORD 1:** +-----------------------+-----------------------------------------------+** |      Phys    |  Rsvd  | Prefetch |Update |Rsvd  |Lock  |Safe  |Valid  |** |     20:39    |        | Enable   |Enable |      |Enable|DMA   |       |** |    20 bits   | 5 bits | 1 bit    |1 bit  |2 bits|1 bit |1 bit |1 bit  |** +-----------------------+-----------------------------------------------+**** The virtual index field is filled with the results of the LCI** (Load Coherence Index) instruction.  The 8 bits used for the virtual** index are bits 12:19 of the value returned by LCI.*/void CCIO_INLINEccio_io_pdir_entry(u64 *pdir_ptr, space_t sid, void * vba, unsigned long hints){	register unsigned long pa = (volatile unsigned long) vba;	register unsigned long ci; /* coherent index */	/* We currently only support kernel addresses */	ASSERT(sid == 0);	ASSERT(((unsigned long) vba & 0xf0000000UL) == 0xc0000000UL);	mtsp(sid,1);	/*	** WORD 1 - low order word	** "hints" parm includes the VALID bit!	** "dep" clobbers the physical address offset bits as well.	*/	pa = virt_to_phys(vba);	asm volatile("depw  %1,31,12,%0" : "+r" (pa) : "r" (hints));	((u32 *)pdir_ptr)[1] = (u32) pa;	/*	** WORD 0 - high order word	*/#ifdef __LP64__	/*	** get bits 12:15 of physical address	** shift bits 16:31 of physical address	** and deposit them	*/	asm volatile ("extrd,u %1,15,4,%0" : "=r" (ci) : "r" (pa));	asm volatile ("extrd,u %1,31,16,%0" : "+r" (ci) : "r" (ci));	asm volatile ("depd  %1,35,4,%0" : "+r" (pa) : "r" (ci));#else	pa = 0;#endif	/*	** get CPU coherency index bits	** Grab virtual index [0:11]	** Deposit virt_idx bits into I/O PDIR word	*/	asm volatile ("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));	asm volatile ("extru %1,19,12,%0" : "+r" (ci) : "r" (ci));	asm volatile ("depw  %1,15,12,%0" : "+r" (pa) : "r" (ci));	((u32 *)pdir_ptr)[0] = (u32) pa;	/* FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360)	**        PCX-U/U+ do. (eg C200/C240)	**        PCX-T'? Don't know. (eg C110 or similar K-class)	**	** See PDC_MODEL/option 0/SW_CAP word for "Non-coherent IO-PDIR bit".	** Hopefully we can patch (NOP) these out at boot time somehow.	**	** "Since PCX-U employs an offset hash that is incompatible with	** the real mode coherence index generation of U2, the PDIR entry	** must be flushed to memory to retain coherence."	*/	asm volatile("fdc 0(%0)" : : "r" (pdir_ptr));	asm volatile("sync");}/*** Remove stale entries from the I/O TLB.** Need to do this whenever an entry in the PDIR is marked invalid.*/static CCIO_INLINE voidccio_clear_io_tlb( struct ccio_device *d, dma_addr_t iovp, size_t byte_cnt){	u32 chain_size = 1 << d->chainid_shift;	iovp &= ~(IOVP_SIZE-1);	/* clear offset bits, just want pagenum */	byte_cnt += chain_size;        while (byte_cnt > chain_size) {		WRITE_U32(CMD_TLB_PURGE | iovp, &d->ccio_hpa->io_command);                iovp += chain_size;		byte_cnt -= chain_size;        }}/*********************************************************** * * Mark the I/O Pdir entries invalid and blow away the * corresponding I/O TLB entries. * * FIXME: at some threshhold it might be "cheaper" to just blow *        away the entire I/O TLB instead of individual entries. * * FIXME: Uturn has 256 TLB entries. We don't need to purge every *        PDIR entry - just once for each possible TLB entry. *        (We do need to maker I/O PDIR entries invalid regardless). ***********************************************************/static CCIO_INLINE voidccio_mark_invalid(struct ccio_device *d, dma_addr_t iova, size_t byte_cnt){	u32 iovp = (u32) CCIO_IOVP(iova);	size_t saved_byte_cnt;	/* round up to nearest page size */	saved_byte_cnt = byte_cnt = (byte_cnt + IOVP_SIZE - 1) & IOVP_MASK;	while (byte_cnt > 0) {		/* invalidate one page at a time */		unsigned int idx = PDIR_INDEX(iovp);		char *pdir_ptr = (char *) &(d->pdir_base[idx]);		ASSERT( idx < (d->pdir_size/sizeof(u64)));		pdir_ptr[7] = 0;	/* clear only VALID bit */		/*		** FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360)		**   PCX-U/U+ do. (eg C200/C240)		** See PDC_MODEL/option 0/SW_CAP for "Non-coherent IO-PDIR bit".		**		** Hopefully someone figures out how to patch (NOP) the		** FDC/SYNC out at boot time.		*/		asm volatile("fdc 0(%0)" : : "r" (pdir_ptr[7]));		iovp     += IOVP_SIZE;		byte_cnt -= IOVP_SIZE;	}	asm volatile("sync");	ccio_clear_io_tlb(d, CCIO_IOVP(iova), saved_byte_cnt);}/********************************************************************          CCIO dma_ops*******************************************************************/void __init ccio_init(void){	register_driver(ccio_drivers_for);}static int ccio_dma_supported( struct pci_dev *dev, dma_addr_t mask){	if (dev == NULL) {		printk(MODULE_NAME ": EISA/ISA/et al not supported\n");		BUG();		return(0);	}	dev->dma_mask = mask;   /* save it */	/* only support 32-bit devices (ie PCI/GSC) */	return((int) (mask >= 0xffffffffUL));}/*** Dump a hex representation of the resource map.*/#ifdef DUMP_RESMAPstatic void dump_resmap(){	struct ccio_device *ioa = ccio_list;	unsigned long *res_ptr = (unsigned long *)ioa->res_map;	unsigned long i = 0;	printk("res_map: ");	for(; i < (ioa->res_size / sizeof(unsigned long)); ++i, ++res_ptr)		printk("%08lx ", *res_ptr);	printk("\n");}#endif/*** map_single returns a fully formed IOVA*/static dma_addr_t ccio_map_single(struct pci_dev *dev, void *addr, size_t size, int direction){	struct ccio_device *ioa = ccio_list;  /* FIXME : see Multi-IOC below */	dma_addr_t iovp;	dma_addr_t offset;	u64 *pdir_start;	unsigned long hint = hint_lookup[direction];	int idx;	ASSERT(size > 0);	/* save offset bits */	offset = ((dma_addr_t) addr) & ~IOVP_MASK;	/* round up to nearest IOVP_SIZE */	size = (size + offset + IOVP_SIZE - 1) & IOVP_MASK;	idx = ccio_alloc_range(ioa, size);	iovp = (dma_addr_t) MKIOVP(idx);	DBG_RUN(__FUNCTION__ " 0x%p -> 0x%lx", addr, (long) iovp | offset);	pdir_start = &(ioa->pdir_base[idx]);	/* If not cacheline aligned, force SAFE_DMA on the whole mess */	if ((size % L1_CACHE_BYTES) || ((unsigned long) addr % L1_CACHE_BYTES))		hint |= HINT_SAFE_DMA;	/* round up to nearest IOVP_SIZE */	size = (size + IOVP_SIZE - 1) & IOVP_MASK;	while (size > 0) {		ccio_io_pdir_entry(pdir_start, KERNEL_SPACE, addr, hint);		DBG_RUN(" pdir %p %08x%08x\n",			pdir_start,			(u32) (((u32 *) pdir_start)[0]),			(u32) (((u32 *) pdir_start)[1])			);		addr += IOVP_SIZE;		size -= IOVP_SIZE;		pdir_start++;	}	/* form complete address */	return CCIO_IOVA(iovp, offset);}static void ccio_unmap_single(struct pci_dev *dev, dma_addr_t iova, size_t size, int direction){#ifdef FIXME/* Multi-IOC (ie N-class) :  need to lookup IOC from dev** o If we can't know about lba PCI data structs, that eliminates ->sysdata.** o walking up pcidev->parent dead ends at elroy too** o leaves hashing dev->bus->number into some lookup.**   (may only work for N-class)*/	struct ccio_device *ioa = dev->sysdata#else	struct ccio_device *ioa = ccio_list;#endif	dma_addr_t offset;		offset = iova & ~IOVP_MASK;	/* round up to nearest IOVP_SIZE */	size = (size + offset + IOVP_SIZE - 1) & IOVP_MASK;	/* Mask off offset */	iova &= IOVP_MASK;	DBG_RUN(__FUNCTION__ " iovp 0x%lx\n", (long) iova);#ifdef DELAYED_RESOURCE_CNT	if (ioa->saved_cnt < DELAYED_RESOURCE_CNT) {		ioa->saved_iova[ioa->saved_cnt] = iova;		ioa->saved_size[ioa->saved_cnt] = size;		ccio_saved_cnt++;	} else {		do {#endif			ccio_mark_invalid(ioa, iova, size);			ccio_free_range(ioa, iova, size);#ifdef DELAYED_RESOURCE_CNT			d->saved_cnt--;			iova = ioa->saved_iova[ioa->saved_cnt];			size = ioa->saved_size[ioa->saved_cnt];		} while (ioa->saved_cnt)	}#endif}static void * ccio_alloc_consistent (struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle){	void *ret;	unsigned long flags;	struct ccio_device *ioa = ccio_list;	DBG_RUN(__FUNCTION__ " size 0x%x\n",  size);#if 0/* GRANT Need to establish hierarchy for non-PCI devs as well** and then provide matching gsc_map_xxx() functions for them as well.*/	if (!hwdev) {		/* only support PCI */		*dma_handle = 0;		return 0;	}#endif	spin_lock_irqsave(&ioa->ccio_lock, flags);	ccio_alloc_size += get_order(size);	spin_unlock_irqrestore(&ioa->ccio_lock, flags);        ret = (void *) __get_free_pages(GFP_ATOMIC, get_order(size));	if (ret) {		memset(ret, 0, size);		*dma_handle = ccio_map_single(hwdev, ret, size, PCI_DMA_BIDIRECTIONAL);	}	DBG_RUN(__FUNCTION__ " ret %p\n",  ret);	return ret;}static void ccio_free_consistent (struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle){