cs->dc.icc.mocr |= 0x0a;					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);					cs->dc.icc.mon_rxp = 0;					if (cs->debug & L1_DEB_WARN)						debugl1(cs, "ICC MON RX overflow!");					goto afterMONR0;				}				cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR0);				if (cs->debug & L1_DEB_MONITOR)					debugl1(cs, "ICC MOR0 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp -1]);				if (cs->dc.icc.mon_rxp == 1) {					cs->dc.icc.mocr |= 0x04;					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);				}			}		      afterMONR0:			if (v1 & 0x80) {				if (!cs->dc.icc.mon_rx) {					if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) {						if (cs->debug & L1_DEB_WARN)							debugl1(cs, "ICC MON RX out of memory!");						cs->dc.icc.mocr &= 0x0f;						cs->dc.icc.mocr |= 0xa0;						cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);						goto afterMONR1;					} else						cs->dc.icc.mon_rxp = 0;				}				if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) {					cs->dc.icc.mocr &= 0x0f;					cs->dc.icc.mocr |= 0xa0;					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);					cs->dc.icc.mon_rxp = 0;					if (cs->debug & L1_DEB_WARN)						debugl1(cs, "ICC MON RX overflow!");					goto afterMONR1;				}				cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR1);				if (cs->debug & L1_DEB_MONITOR)					debugl1(cs, "ICC MOR1 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp -1]);				cs->dc.icc.mocr |= 0x40;				cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);			}		      afterMONR1:			if (v1 & 0x04) {				cs->dc.icc.mocr &= 0xf0;				cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);				cs->dc.icc.mocr |= 0x0a;				cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);				icc_sched_event(cs, D_RX_MON0);			}			if (v1 & 0x40) {				cs->dc.icc.mocr &= 0x0f;				cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);				cs->dc.icc.mocr |= 0xa0;				cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);				icc_sched_event(cs, D_RX_MON1);			}			if (v1 & 0x02) {				if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc && 					(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) && 					!(v1 & 0x08))) {					cs->dc.icc.mocr &= 0xf0;					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);					cs->dc.icc.mocr |= 0x0a;					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);					if (cs->dc.icc.mon_txc &&						(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))						icc_sched_event(cs, D_TX_MON0);					goto AfterMOX0;				}				if (cs->dc.icc.mon_txc && (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) {					icc_sched_event(cs, D_TX_MON0);					goto AfterMOX0;				}				cs->writeisac(cs, ICC_MOX0,					cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);				if (cs->debug & L1_DEB_MONITOR)					debugl1(cs, "ICC %02x -> MOX0", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp -1]);			}		      AfterMOX0:			if (v1 & 0x20) {				if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc && 					(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) && 					!(v1 & 0x80))) {					cs->dc.icc.mocr &= 0x0f;					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);					cs->dc.icc.mocr |= 0xa0;					cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);					if (cs->dc.icc.mon_txc &&						(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))						icc_sched_event(cs, D_TX_MON1);					goto AfterMOX1;				}				if (cs->dc.icc.mon_txc && (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) {					icc_sched_event(cs, D_TX_MON1);					goto AfterMOX1;				}				cs->writeisac(cs, ICC_MOX1,					cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);				if (cs->debug & L1_DEB_MONITOR)					debugl1(cs, "ICC %02x -> MOX1", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp -1]);			}		      AfterMOX1:#endif		}	}}static voidICC_l1hw(struct PStack *st, int pr, void *arg){	struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;	struct sk_buff *skb = arg;	int  val;	switch (pr) {		case (PH_DATA |REQUEST):			if (cs->debug & DEB_DLOG_HEX)				LogFrame(cs, skb->data, skb->len);			if (cs->debug & DEB_DLOG_VERBOSE)				dlogframe(cs, skb, 0);			if (cs->tx_skb) {				skb_queue_tail(&cs->sq, skb);#ifdef L2FRAME_DEBUG		/* psa */				if (cs->debug & L1_DEB_LAPD)					Logl2Frame(cs, skb, "PH_DATA Queued", 0);#endif			} else {				cs->tx_skb = skb;				cs->tx_cnt = 0;#ifdef L2FRAME_DEBUG		/* psa */				if (cs->debug & L1_DEB_LAPD)					Logl2Frame(cs, skb, "PH_DATA", 0);#endif				icc_fill_fifo(cs);			}			break;		case (PH_PULL |INDICATION):			if (cs->tx_skb) {				if (cs->debug & L1_DEB_WARN)					debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");				skb_queue_tail(&cs->sq, skb);				break;			}			if (cs->debug & DEB_DLOG_HEX)				LogFrame(cs, skb->data, skb->len);			if (cs->debug & DEB_DLOG_VERBOSE)				dlogframe(cs, skb, 0);			cs->tx_skb = skb;			cs->tx_cnt = 0;#ifdef L2FRAME_DEBUG		/* psa */			if (cs->debug & L1_DEB_LAPD)				Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);#endif			icc_fill_fifo(cs);			break;		case (PH_PULL | REQUEST):#ifdef L2FRAME_DEBUG		/* psa */			if (cs->debug & L1_DEB_LAPD)				debugl1(cs, "-> PH_REQUEST_PULL");#endif			if (!cs->tx_skb) {				test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);				st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);			} else				test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);			break;		case (HW_RESET | REQUEST):			if ((cs->dc.icc.ph_state == ICC_IND_EI1) ||				(cs->dc.icc.ph_state == ICC_IND_DR))			        ph_command(cs, ICC_CMD_DI);			else				ph_command(cs, ICC_CMD_RES);			break;		case (HW_ENABLE | REQUEST):			ph_command(cs, ICC_CMD_DI);			break;		case (HW_INFO1 | REQUEST):			ph_command(cs, ICC_CMD_AR);			break;		case (HW_INFO3 | REQUEST):			ph_command(cs, ICC_CMD_AI);			break;		case (HW_TESTLOOP | REQUEST):			val = 0;			if (1 & (long) arg)				val |= 0x0c;			if (2 & (long) arg)				val |= 0x3;			if (test_bit(HW_IOM1, &cs->HW_Flags)) {				/* IOM 1 Mode */				if (!val) {					cs->writeisac(cs, ICC_SPCR, 0xa);					cs->writeisac(cs, ICC_ADF1, 0x2);				} else {					cs->writeisac(cs, ICC_SPCR, val);					cs->writeisac(cs, ICC_ADF1, 0xa);				}			} else {				/* IOM 2 Mode */				cs->writeisac(cs, ICC_SPCR, val);				if (val)					cs->writeisac(cs, ICC_ADF1, 0x8);				else					cs->writeisac(cs, ICC_ADF1, 0x0);			}			break;		case (HW_DEACTIVATE | RESPONSE):			discard_queue(&cs->rq);			discard_queue(&cs->sq);			if (cs->tx_skb) {				dev_kfree_skb_any(cs->tx_skb);				cs->tx_skb = NULL;			}			if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))				del_timer(&cs->dbusytimer);			if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))				icc_sched_event(cs, D_CLEARBUSY);			break;		default:			if (cs->debug & L1_DEB_WARN)				debugl1(cs, "icc_l1hw unknown %04x", pr);			break;	}}voidsetstack_icc(struct PStack *st, struct IsdnCardState *cs){	st->l1.l1hw = ICC_l1hw;}void DC_Close_icc(struct IsdnCardState *cs) {	if (cs->dc.icc.mon_rx) {		kfree(cs->dc.icc.mon_rx);		cs->dc.icc.mon_rx = NULL;	}	if (cs->dc.icc.mon_tx) {		kfree(cs->dc.icc.mon_tx);		cs->dc.icc.mon_tx = NULL;	}}static voiddbusy_timer_handler(struct IsdnCardState *cs){	struct PStack *stptr;	int	rbch, star;	if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {		rbch = cs->readisac(cs, ICC_RBCH);		star = cs->readisac(cs, ICC_STAR);		if (cs->debug) 			debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x",				rbch, star);		if (rbch & ICC_RBCH_XAC) { /* D-Channel Busy */			test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags);			stptr = cs->stlist;			while (stptr != NULL) {				stptr->l1.l1l2(stptr, PH_PAUSE | INDICATION, NULL);				stptr = stptr->next;			}		} else {			/* discard frame; reset transceiver */			test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);			if (cs->tx_skb) {				dev_kfree_skb_any(cs->tx_skb);				cs->tx_cnt = 0;				cs->tx_skb = NULL;			} else {				printk(KERN_WARNING "HiSax: ICC D-Channel Busy no skb\n");				debugl1(cs, "D-Channel Busy no skb");			}			cs->writeisac(cs, ICC_CMDR, 0x01); /* Transmitter reset */			cs->irq_func(cs->irq, cs, NULL);		}	}}void __initiniticc(struct IsdnCardState *cs){	cs->tqueue.routine = (void *) (void *) icc_bh;	cs->setstack_d = setstack_icc;	cs->DC_Close = DC_Close_icc;	cs->dc.icc.mon_tx = NULL;	cs->dc.icc.mon_rx = NULL;	cs->dbusytimer.function = (void *) dbusy_timer_handler;	cs->dbusytimer.data = (long) cs;	init_timer(&cs->dbusytimer);  	cs->writeisac(cs, ICC_MASK, 0xff);  	cs->dc.icc.mocr = 0xaa;	if (test_bit(HW_IOM1, &cs->HW_Flags)) {		/* IOM 1 Mode */		cs->writeisac(cs, ICC_ADF2, 0x0);		cs->writeisac(cs, ICC_SPCR, 0xa);		cs->writeisac(cs, ICC_ADF1, 0x2);		cs->writeisac(cs, ICC_STCR, 0x70);		cs->writeisac(cs, ICC_MODE, 0xc9);	} else {		/* IOM 2 Mode */		if (!cs->dc.icc.adf2)			cs->dc.icc.adf2 = 0x80;		cs->writeisac(cs, ICC_ADF2, cs->dc.icc.adf2);		cs->writeisac(cs, ICC_SQXR, 0xa0);		cs->writeisac(cs, ICC_SPCR, 0x20);		cs->writeisac(cs, ICC_STCR, 0x70);		cs->writeisac(cs, ICC_MODE, 0xca);		cs->writeisac(cs, ICC_TIMR, 0x00);		cs->writeisac(cs, ICC_ADF1, 0x20);	}	ph_command(cs, ICC_CMD_RES);	cs->writeisac(cs, ICC_MASK, 0x0);	ph_command(cs, ICC_CMD_DI);}void __initclear_pending_icc_ints(struct IsdnCardState *cs){	int val, eval;	val = cs->readisac(cs, ICC_STAR);	debugl1(cs, "ICC STAR %x", val);	val = cs->readisac(cs, ICC_MODE);	debugl1(cs, "ICC MODE %x", val);	val = cs->readisac(cs, ICC_ADF2);	debugl1(cs, "ICC ADF2 %x", val);	val = cs->readisac(cs, ICC_ISTA);	debugl1(cs, "ICC ISTA %x", val);	if (val & 0x01) {		eval = cs->readisac(cs, ICC_EXIR);		debugl1(cs, "ICC EXIR %x", eval);	}	val = cs->readisac(cs, ICC_CIR0);	debugl1(cs, "ICC CIR0 %x", val);	cs->dc.icc.ph_state = (val >> 2) & 0xf;	icc_sched_event(cs, D_L1STATECHANGE);	/* Disable all IRQ */	cs->writeisac(cs, ICC_MASK, 0xFF);}