*/			wv		: 1,	/* Way field valid */			op		: 3,	/* Type of cache 						 * operation that 						 * caused the machine						 * check.						 */			dl		: 1,	/* Failure in data part						 * of cache line						 */			tl		: 1,	/* Failure in tag part						 * of cache line						 */			dc		: 1,	/* Failure in dcache */			ic		: 1,	/* Failure in icache */			index		: 24,	/* Cache line index */			mv		: 1,	/* mesi valid */			mesi		: 3,	/* Cache line state */			level		: 4;	/* Cache level */} pal_cache_check_info_t;typedef struct pal_tlb_check_info_s {	u64		tr_slot		: 8,	/* Slot# of TR where						 * error occurred 						 */			reserved2	: 8,			dtr		: 1,	/* Fail in data TR */			itr		: 1,	/* Fail in inst TR */			dtc		: 1,	/* Fail in data TC */			itc		: 1,	/* Fail in inst. TC */			mc		: 1,	/* Machine check corrected */			reserved1	: 43;} pal_tlb_check_info_t;typedef struct pal_bus_check_info_s {	u64		size		: 5,	/* Xaction size*/			ib		: 1,	/* Internal bus error */			eb		: 1,	/* External bus error */			cc		: 1,	/* Error occurred 						 * during cache-cache						 * transfer.						 */			type		: 8,	/* Bus xaction type*/			sev		: 5,	/* Bus error severity*/			tv		: 1,	/* Targ addr valid */			rp		: 1,	/* Resp addr valid */			rq		: 1,	/* Req addr valid */			bsi		: 8,	/* Bus error status 						 * info						 */			mc		: 1,	/* Machine check corrected */			reserved1	: 31;} pal_bus_check_info_t;typedef union pal_mc_error_info_u {	u64				pmei_data;	pal_processor_state_info_t	pme_processor;	pal_cache_check_info_t		pme_cache;	pal_tlb_check_info_t		pme_tlb;	pal_bus_check_info_t		pme_bus;} pal_mc_error_info_t;#define pmci_proc_unknown_check			pme_processor.uc#define pmci_proc_bus_check			pme_processor.bc#define pmci_proc_tlb_check			pme_processor.tc#define pmci_proc_cache_check			pme_processor.cc#define pmci_proc_dynamic_state_size		pme_processor.dsize#define pmci_proc_gpr_valid			pme_processor.gr#define pmci_proc_preserved_bank0_gpr_valid	pme_processor.b0#define pmci_proc_preserved_bank1_gpr_valid	pme_processor.b1#define pmci_proc_fp_valid			pme_processor.fp#define pmci_proc_predicate_regs_valid		pme_processor.pr#define pmci_proc_branch_regs_valid		pme_processor.br#define pmci_proc_app_regs_valid		pme_processor.ar#define pmci_proc_region_regs_valid		pme_processor.rr#define pmci_proc_translation_regs_valid	pme_processor.tr#define pmci_proc_debug_regs_valid		pme_processor.dr#define pmci_proc_perf_counters_valid		pme_processor.pc#define pmci_proc_control_regs_valid		pme_processor.cr#define pmci_proc_machine_check_expected	pme_processor.ex#define pmci_proc_machine_check_corrected	pme_processor.cm#define pmci_proc_rse_valid			pme_processor.rs#define pmci_proc_machine_check_or_init		pme_processor.in#define pmci_proc_dynamic_state_valid		pme_processor.dy#define pmci_proc_operation			pme_processor.op#define pmci_proc_trap_lost			pme_processor.tl#define pmci_proc_hardware_damage		pme_processor.hd#define pmci_proc_uncontained_storage_damage	pme_processor.us#define pmci_proc_machine_check_isolated	pme_processor.ci#define pmci_proc_continuable			pme_processor.co#define pmci_proc_storage_intergrity_synced	pme_processor.sy#define pmci_proc_min_state_save_area_regd	pme_processor.mn#define	pmci_proc_distinct_multiple_errors	pme_processor.me#define pmci_proc_pal_attempted_rendezvous	pme_processor.ra#define pmci_proc_pal_rendezvous_complete	pme_processor.rz#define pmci_cache_level			pme_cache.level#define pmci_cache_line_state			pme_cache.mesi#define pmci_cache_line_state_valid		pme_cache.mv#define pmci_cache_line_index			pme_cache.index#define pmci_cache_instr_cache_fail		pme_cache.ic#define pmci_cache_data_cache_fail		pme_cache.dc#define pmci_cache_line_tag_fail		pme_cache.tl#define pmci_cache_line_data_fail		pme_cache.dl#define pmci_cache_operation			pme_cache.op#define pmci_cache_way_valid			pme_cache.wv#define pmci_cache_target_address_valid		pme_cache.tv#define pmci_cache_way				pme_cache.way#define pmci_cache_mc				pme_cache.mc#define pmci_tlb_instr_translation_cache_fail	pme_tlb.itc#define pmci_tlb_data_translation_cache_fail	pme_tlb.dtc#define pmci_tlb_instr_translation_reg_fail	pme_tlb.itr#define pmci_tlb_data_translation_reg_fail	pme_tlb.dtr#define pmci_tlb_translation_reg_slot		pme_tlb.tr_slot#define pmci_tlb_mc				pme_tlb.mc#define pmci_bus_status_info			pme_bus.bsi#define pmci_bus_req_address_valid		pme_bus.rq#define pmci_bus_resp_address_valid		pme_bus.rp#define pmci_bus_target_address_valid		pme_bus.tv#define pmci_bus_error_severity			pme_bus.sev#define pmci_bus_transaction_type		pme_bus.type#define pmci_bus_cache_cache_transfer		pme_bus.cc#define pmci_bus_transaction_size		pme_bus.size#define pmci_bus_internal_error			pme_bus.ib#define pmci_bus_external_error			pme_bus.eb#define pmci_bus_mc				pme_bus.mc/*  * NOTE: this min_state_save area struct only includes the 1KB  * architectural state save area.  The other 3 KB is scratch space * for PAL. */typedef struct pal_min_state_area_s {	u64	pmsa_nat_bits;		/* nat bits for saved GRs  */	u64	pmsa_gr[15];		/* GR1	- GR15		   */	u64	pmsa_bank0_gr[16];	/* GR16 - GR31		   */	u64	pmsa_bank1_gr[16];	/* GR16 - GR31		   */	u64	pmsa_pr;		/* predicate registers	   */	u64	pmsa_br0;		/* branch register 0	   */	u64	pmsa_rsc;		/* ar.rsc		   */	u64	pmsa_iip;		/* cr.iip		   */	u64	pmsa_ipsr;		/* cr.ipsr		   */	u64	pmsa_ifs;		/* cr.ifs		   */	u64	pmsa_xip;		/* previous iip		   */	u64	pmsa_xpsr;		/* previous psr		   */	u64	pmsa_xfs;		/* previous ifs		   */	u64	pmsa_reserved[71];	/* pal_min_state_area should total to 1KB */} pal_min_state_area_t;struct ia64_pal_retval {	/*	 * A zero status value indicates call completed without error.	 * A negative status value indicates reason of call failure.	 * A positive status value indicates success but an	 * informational value should be printed (e.g., "reboot for	 * change to take effect").	 */	s64 status;	u64 v0;	u64 v1;	u64 v2;};/* * Note: Currently unused PAL arguments are generally labeled * "reserved" so the value specified in the PAL documentation * (generally 0) MUST be passed.  Reserved parameters are not optional * parameters. */extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64);extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);#define PAL_CALL(iprv,a0,a1,a2,a3)		iprv = ia64_pal_call_static(a0, a1, a2, a3, 0)#define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3)	iprv = ia64_pal_call_static(a0, a1, a2, a3, 1)#define PAL_CALL_STK(iprv,a0,a1,a2,a3)		iprv = ia64_pal_call_stacked(a0, a1, a2, a3)#define PAL_CALL_PHYS(iprv,a0,a1,a2,a3)		iprv = ia64_pal_call_phys_static(a0, a1, a2, a3)#define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3)	iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3)typedef int (*ia64_pal_handler) (u64, ...);extern ia64_pal_handler ia64_pal;extern void ia64_pal_handler_init (void *);extern ia64_pal_handler ia64_pal;extern pal_cache_config_info_t		l0d_cache_config_info;extern pal_cache_config_info_t		l0i_cache_config_info;extern pal_cache_config_info_t		l1_cache_config_info;extern pal_cache_config_info_t		l2_cache_config_info;extern pal_cache_protection_info_t	l0d_cache_protection_info;extern pal_cache_protection_info_t	l0i_cache_protection_info;extern pal_cache_protection_info_t	l1_cache_protection_info;extern pal_cache_protection_info_t	l2_cache_protection_info;extern pal_cache_config_info_t		pal_cache_config_info_get(pal_cache_level_t,								  pal_cache_type_t);extern pal_cache_protection_info_t	pal_cache_protection_info_get(pal_cache_level_t,								      pal_cache_type_t);extern void				pal_error(int);/* Useful wrappers for the current list of pal procedures */typedef union pal_bus_features_u {	u64	pal_bus_features_val;	struct {		u64	pbf_reserved1				:	29;		u64	pbf_req_bus_parking			:	1;		u64	pbf_bus_lock_mask			:	1;		u64	pbf_enable_half_xfer_rate		:	1;		u64	pbf_reserved2				:	22;		u64	pbf_disable_xaction_queueing		:	1;		u64	pbf_disable_resp_err_check		:	1;		u64	pbf_disable_berr_check			:	1;		u64	pbf_disable_bus_req_internal_err_signal	:	1;		u64	pbf_disable_bus_req_berr_signal		:	1;		u64	pbf_disable_bus_init_event_check	:	1;		u64	pbf_disable_bus_init_event_signal	:	1;		u64	pbf_disable_bus_addr_err_check		:	1;		u64	pbf_disable_bus_addr_err_signal		:	1;		u64	pbf_disable_bus_data_err_check		:	1;	} pal_bus_features_s;} pal_bus_features_u_t; extern void pal_bus_features_print (u64);/* Provide information about configurable processor bus features */static inline s64 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,			   pal_bus_features_u_t *features_status,			   pal_bus_features_u_t *features_control){	struct ia64_pal_retval iprv;	PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);	if (features_avail)		features_avail->pal_bus_features_val = iprv.v0;	if (features_status)		features_status->pal_bus_features_val = iprv.v1;	if (features_control)		features_control->pal_bus_features_val = iprv.v2;	return iprv.status;	}/* Enables/disables specific processor bus features */static inline s64 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select) {		struct ia64_pal_retval iprv;	PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);	return iprv.status;}/* Get detailed cache information */static inline s64ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0); 	if (iprv.status == 0) {		conf->pcci_status                 = iprv.status;		conf->pcci_info_1.pcci1_data      = iprv.v0;		conf->pcci_info_2.pcci2_data      = iprv.v1;		conf->pcci_reserved               = iprv.v2;	}	return iprv.status; }/* Get detailed cche protection information */static inline s64ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0); 	if (iprv.status == 0) {		prot->pcpi_status           = iprv.status;		prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;		prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;		prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;		prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;		prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;		prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;	}	return iprv.status; } /* * Flush the processor instruction or data caches.  *PROGRESS must be * initialized to zero before calling this for the first time.. */static inline s64 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress) {		struct ia64_pal_retval iprv;	PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress); 	*progress = iprv.v1;	return iprv.status; }/* Initialize the processor controlled caches */static inline s64 ia64_pal_cache_init (u64 level, u64 cache_type, u64 restrict) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, restrict); 	return iprv.status; }/* Initialize the tags and data of a data or unified cache line of  * processor controlled cache to known values without the availability  * of backing memory. */static inline s64 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);	return iprv.status; }/* Read the data and tag of a processor controlled cache line for diags */static inline s64 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0);	return iprv.status; }/* Return summary information about the heirarchy of caches controlled by the processor */static inline s64 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);	if (cache_levels)		*cache_levels = iprv.v0;	if (unique_caches)		*unique_caches = iprv.v1;	return iprv.status; }/* Write the data and tag of a processor-controlled cache line for diags */static inline s64 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data) {		struct ia64_pal_retval iprv;		PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data);	return iprv.status; }/* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */static inline s64 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,		    u64 *buffer_size, u64 *buffer_align) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics); 	if (buffer_size)		*buffer_size = iprv.v0;	if (buffer_align)		*buffer_align = iprv.v1;	return iprv.status; }/* Copy relocatable PAL procedures from ROM to memory */static inline s64 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);	if (pal_proc_offset)		*pal_proc_offset = iprv.v0;	return iprv.status; }/* Return the number of instruction and data debug register pairs */static inline s64 ia64_pal_debug_info (u64 *inst_regs,  u64 *data_regs) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);	if (inst_regs)		*inst_regs = iprv.v0;	if (data_regs)		*data_regs = iprv.v1;	return iprv.status; }#ifdef TBD/* Switch from IA64-system environment to IA-32 system environment */static inline s64 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3); 	return iprv.status; }#endif/* Get unique geographical address of this processor on its bus */static inline s64 ia64_pal_fixed_addr (u64 *global_unique_addr) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);	if (global_unique_addr)		*global_unique_addr = iprv.v0;	return iprv.status; }/* Get base frequency of the platform if generated by the processor */static inline s64 ia64_pal_freq_base (u64 *platform_base_freq) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);	if (platform_base_freq)		*platform_base_freq = iprv.v0;	return iprv.status; }/* * Get the ratios for processor frequency, bus frequency and interval timer to * to base frequency of the platform  */static inline s64 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,		      struct pal_freq_ratio *itc_ratio) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);	if (proc_ratio)		*(u64 *)proc_ratio = iprv.v0;	if (bus_ratio)		*(u64 *)bus_ratio = iprv.v1;	if (itc_ratio)		*(u64 *)itc_ratio = iprv.v2;	return iprv.status; }/* Make the processor enter HALT or one of the implementation dependent low  * power states where prefetching and execution are suspended and cache and * TLB coherency is not maintained. */