static inline s64 ia64_pal_halt (u64 halt_state) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);	return iprv.status; }typedef union pal_power_mgmt_info_u {	u64			ppmi_data;	struct {	       u64		exit_latency		: 16,				entry_latency		: 16,				power_consumption	: 28,				im			: 1,				co			: 1,				reserved		: 2;	} pal_power_mgmt_info_s;} pal_power_mgmt_info_u_t;/* Return information about processor's optional power management capabilities. */static inline s64 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf) {		struct ia64_pal_retval iprv;	PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);	return iprv.status; }/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are * suspended, but cache and TLB coherency is maintained. */static inline s64 ia64_pal_halt_light (void) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);	return iprv.status; }/* Clear all the processor error logging   registers and reset the indicator that allows * the error logging registers to be written. This procedure also checks the pending * machine check bit and pending INIT bit and reports their states. */static inline s64 ia64_pal_mc_clear_log (u64 *pending_vector) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);	if (pending_vector)		*pending_vector = iprv.v0;	return iprv.status; }/* Ensure that all outstanding transactions in a processor are completed or that any  * MCA due to thes outstanding transaction is taken. */static inline s64 ia64_pal_mc_drain (void) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);	return iprv.status; }/* Return the machine check dynamic processor state */static inline s64 ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);	if (size)		*size = iprv.v0;	if (pds)		*pds = iprv.v1;	return iprv.status; }/* Return processor machine check information */static inline s64 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);	if (size)		*size = iprv.v0;	if (error_info)		*error_info = iprv.v1;		return iprv.status; }/* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot * attempt to correct any expected machine checks. */static inline s64 ia64_pal_mc_expected (u64 expected, u64 *previous) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);	if (previous)		*previous = iprv.v0;	return iprv.status; }/* Register a platform dependent location with PAL to which it can save * minimal processor state in the event of a machine check or initialization * event. */static inline s64ia64_pal_mc_register_mem (u64 physical_addr) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);	return iprv.status; }/* Restore minimal architectural processor state, set CMC interrupt if necessary * and resume execution */static inline s64 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);	return iprv.status; }/* Return the memory attributes implemented by the processor */static inline s64 ia64_pal_mem_attrib (u64 *mem_attrib) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);	if (mem_attrib)		*mem_attrib = iprv.v0 & 0xff;	return iprv.status; }/* Return the amount of memory needed for second phase of processor * self-test and the required alignment of memory. */static inline s64 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);	if (bytes_needed)		*bytes_needed = iprv.v0;	if (alignment)		*alignment = iprv.v1;	return iprv.status; }typedef union pal_perf_mon_info_u {	u64			  ppmi_data;	struct {	       u64		generic		: 8,	       			width		: 8,		       		cycles		: 8,				retired		: 8,				reserved	: 32;	} pal_perf_mon_info_s;} pal_perf_mon_info_u_t;	       /* Return the performance monitor information about what can be counted * and how to configure the monitors to count the desired events. */static inline s64 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);	if (pm_info)		pm_info->ppmi_data = iprv.v0;	return iprv.status; }/* Specifies the physical address of the processor interrupt block * and I/O port space. */static inline s64 ia64_pal_platform_addr (u64 type, u64 physical_addr) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);	return iprv.status; }/* Set the SAL PMI entrypoint in memory */static inline s64 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);	return iprv.status; }struct pal_features_s;/* Provide information about configurable processor features */static inline s64 ia64_pal_proc_get_features (u64 *features_avail, 			    u64 *features_status, 			    u64 *features_control){		struct ia64_pal_retval iprv;	PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);	if (iprv.status == 0) {		*features_avail   = iprv.v0;		*features_status  = iprv.v1;		*features_control = iprv.v2;	}	return iprv.status; }/* Enable/disable processor dependent features */static inline s64 ia64_pal_proc_set_features (u64 feature_select) {		struct ia64_pal_retval iprv;	PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);	return iprv.status; }/* * Put everything in a struct so we avoid the global offset table whenever * possible. */typedef struct ia64_ptce_info_s {	u64		base;	u32 		count[2];	u32		stride[2];} ia64_ptce_info_t;/* Return the information required for the architected loop used to purge * (initialize) the entire TC */static inline s64ia64_get_ptce (ia64_ptce_info_t *ptce){	struct ia64_pal_retval iprv;	if (!ptce)		return -1;	PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);	if (iprv.status == 0) {		ptce->base = iprv.v0;		ptce->count[0] = iprv.v1 >> 32;		ptce->count[1] = iprv.v1 & 0xffffffff;		ptce->stride[0] = iprv.v2 >> 32;		ptce->stride[1] = iprv.v2 & 0xffffffff;	}	return iprv.status;}/* Return info about implemented application and control registers. */static inline s64 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);	if (reg_info_1)		*reg_info_1 = iprv.v0;	if (reg_info_2)		*reg_info_2 = iprv.v1;	return iprv.status;}	typedef union pal_hints_u {	u64			ph_data;	struct {	       u64		si		: 1,				li		: 1,				reserved	: 62;	} pal_hints_s;} pal_hints_u_t;/* Return information about the register stack and RSE for this processor  * implementation. */static inline s64 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints){		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);	if (num_phys_stacked)		*num_phys_stacked = iprv.v0;	if (hints)		hints->ph_data = iprv.v1;	return iprv.status;	}/* Cause the processor to enter	SHUTDOWN state, where prefetching and execution are  * suspended, but cause cache and TLB coherency to be maintained. * This is usually called in IA-32 mode. */static inline s64 ia64_pal_shutdown (void) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);	return iprv.status; }/* Perform the second phase of processor self-test. */static inline s64 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);	if (self_test_state)		*self_test_state = iprv.v0;	return iprv.status; }typedef union  pal_version_u {	u64	pal_version_val;	struct {		u64	pv_pal_b_rev 		: 	8;		u64	pv_pal_b_model		:	8;		u64	pv_reserved1		:	8;		u64	pv_pal_vendor		:	8;		u64	pv_pal_a_rev		:	8;		u64	pv_pal_a_model		:	8;		u64	pv_reserved2		: 	16;	} pal_version_s;} pal_version_u_t;/* Return PAL version information */static inline s64 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_VERSION, 0, 0, 0);	if (pal_min_version)		pal_min_version->pal_version_val = iprv.v0;	if (pal_cur_version)		pal_cur_version->pal_version_val = iprv.v1;	return iprv.status; }typedef union pal_tc_info_u {	u64			pti_val;	struct {	       u64		num_sets	:	8,				associativity	:	8,				num_entries	:	16,				pf		:	1,				unified		:	1,				reduce_tr	:	1,				reserved	:	29;	} pal_tc_info_s;} pal_tc_info_u_t;								#define tc_reduce_tr		pal_tc_info_s.reduce_tr#define tc_unified		pal_tc_info_s.unified#define tc_pf			pal_tc_info_s.pf#define tc_num_entries		pal_tc_info_s.num_entries#define tc_associativity	pal_tc_info_s.associativity#define tc_num_sets		pal_tc_info_s.num_sets/* Return information about the virtual memory characteristics of the processor  * implementation. */static inline s64 ia64_pal_vm_info (u64 tc_level, u64 tc_type,  pal_tc_info_u_t *tc_info, u64 *tc_pages){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);	if (tc_info)		tc_info->pti_val = iprv.v0;	if (tc_pages)		*tc_pages = iprv.v1;		return iprv.status; }/* Get page size information about the virtual memory characteristics of the processor  * implementation. */static inline s64 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);	if (tr_pages)		*tr_pages = iprv.v0;	if (vw_pages)		*vw_pages = iprv.v1;		return iprv.status; }typedef union pal_vm_info_1_u {	u64			pvi1_val;	struct {		u64		vw		: 1,				phys_add_size	: 7,				key_size	: 8,				max_pkr		: 8,				hash_tag_id	: 8,				max_dtr_entry	: 8,				max_itr_entry	: 8,				max_unique_tcs	: 8,				num_tc_levels	: 8;	} pal_vm_info_1_s;} pal_vm_info_1_u_t;typedef union pal_vm_info_2_u {	u64			pvi2_val;	struct {		u64		impl_va_msb	: 8,				rid_size	: 8,				reserved	: 48;			} pal_vm_info_2_s;} pal_vm_info_2_u_t;		/* Get summary information about the virtual memory characteristics of the processor  * implementation. */static inline s64 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2) {		struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);	if (vm_info_1)		vm_info_1->pvi1_val = iprv.v0;	if (vm_info_2)		vm_info_2->pvi2_val = iprv.v1;	return iprv.status; }typedef union pal_itr_valid_u {	u64			piv_val;	struct {	       u64		access_rights_valid	: 1,				priv_level_valid	: 1,				dirty_bit_valid		: 1,				mem_attr_valid		: 1,				reserved		: 60;	} pal_tr_valid_s;} pal_tr_valid_u_t;/* Read a translation register */static inline s64 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid){	struct ia64_pal_retval iprv;	PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)__pa(tr_buffer));	if (tr_valid)		tr_valid->piv_val = iprv.v0;	return iprv.status; }static inline s64ia64_pal_prefetch_visibility (void){	struct ia64_pal_retval iprv;	PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, 0, 0, 0);	return iprv.status;}#endif /* __ASSEMBLY__ */#endif /* _ASM_IA64_PAL_H */