//
    return(true);
}

//*****************************************************************************
//
// Determines which daughter board is currently attached to the lm3s9b96
// development board and returns the daughter board's information block as
//
// This function determines which of the possible daughter boards are
// attached to the lm3s9b96.  It recognizes Flash/SRAM and FPGA daughter
// boards, each of which contains an I2C device which may be queried to
// identify the board.  In cases where the SDRAM daughter board is attached,
// this function will return \b NONE and the determination of whether or not
// the board is present is left to function SDRAMInit() in extram.c.
//
// \return Returns \b DAUGHTER_FPGA if the FPGA daugher is detected, \b
// DAUGHTER_SRAM_FLASH if the SRAM and flash board is detected and \b
// DAUGHTER_NONE if not board could be identified (covering the cases where
// either no board or the SDRAM board is attached).
//
//*****************************************************************************
static tDaughterBoard
DaughterBoardTypeGet(tDaughterIDInfo *psInfo)
{
    tBoolean bRetcode;

    //
    // Enable the I2C controller used to interface to the daughter board ID
    // EEPROM (if present).
    //
    SysCtlPeripheralEnable(ID_I2C_PERIPH);

    //
    // Configure the I2C SCL and SDA pins for I2C operation.
    //
    GPIOPinTypeI2C(ID_I2CSCL_GPIO_PORT, ID_I2CSCL_PIN | ID_I2CSDA_PIN);

    //
    // Initialize the I2C master.
    //
    I2CMasterInitExpClk(ID_I2C_MASTER_BASE, SysCtlClockGet(), 0);

    //
    // Read the ID information from the I2C EEPROM.
    //
    bRetcode = EEPROMReadPolled((unsigned char *)psInfo, 0,
                                sizeof(tDaughterIDInfo));

    //
    // Did we read the ID information successfully?
    //
    if(bRetcode)
    {
        //
        // Yes.  Check that the structure marker is what we expect.
        //
        if((psInfo->pucMarker[0] == 'I') && (psInfo->pucMarker[1] == 'D'))
        {
            //
            // Marker is fine.
            //
            switch(psInfo->usBoardID)
            {
                //
                // Is this a daughter board we know about already?
                //
                case DAUGHTER_SRAM_FLASH:
                {
                    //
                    // Yes - return the board ID.
                    //
                    return((tDaughterBoard)psInfo->usBoardID);
                }

                //
                // This is a daughter board that we don't know about.
                //
                default:
                {
                    return(DAUGHTER_UNKNOWN);
                }
            }
        }
    }

    //
    // We experienced an error reading the ID EEPROM or read no valid info
    // structure from the device.  This likely indicates that no daughter
    // board is present.  Set the return structure to configure the system
    // assuming that the default (SDRAM) daughter board is present.
    //
    psInfo->usBoardID = (unsigned short)DAUGHTER_NONE;
    psInfo->ulEPIPins = EPI_PINS_SDRAM;
    psInfo->ucEPIMode = EPI_MODE_SDRAM;
    psInfo->ulConfigFlags = (EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_64MBIT);
    psInfo->ucAddrMap = (EPI_ADDR_RAM_SIZE_256MB | EPI_ADDR_RAM_BASE_6);
    psInfo->usRate0nS = 20;
    psInfo->usRate1nS = 20;
    psInfo->ucRefreshInterval = 64;
    psInfo->usNumRows = 4096;
    return(DAUGHTER_NONE);
}


//*****************************************************************************
//
// Given the system clock rate and a desired EPI rate, calculate the divider
// necessary to set the EPI clock at or lower than but as close as possible to
// the desired rate.  The divider is returned and the desired rate is updated
// to give the actual EPI clock rate (in nanoseconds) that will result from
// the use of the calculated divider.
//
//*****************************************************************************
static unsigned short
EPIDividerFromRate(unsigned short *pusDesiredRate, unsigned long ulClknS)
{
    unsigned long ulDivider, ulDesired;

    //
    // If asked for an EPI clock that is at or above the system clock rate,
    // set the divider to 0 and update the EPI rate to match the system clock
    // rate.
    //
    if((unsigned long)*pusDesiredRate <= ulClknS)
    {
        *pusDesiredRate = (unsigned short)ulClknS;
        return(0);
    }

    //
    // The desired EPI rate is slower than the system clock so determine
    // the divider value to use to achieve this as best we can.  The divider
    // generates the EPI clock using the following formula:
    //
    //                     System Clock
    // EPI Clock =   -----------------------
    //                ((Divider/2) + 1) * 2
    //
    // The formula for ulDivider below is determined by reforming this
    // equation and including a (ulClknS - 1) term to ensure that we round
    // the correct way, generating an EPI clock that is never faster than
    // the requested rate.
    //
    ulDesired = (unsigned long)*pusDesiredRate;
    ulDivider = 2 * ((((ulDesired + (ulClknS - 1)) / ulClknS) / 2) - 1) + 1;

    //
    // Now calculate the actual EPI clock period based on the divider we
    // just chose.
    //
    *pusDesiredRate = (unsigned short)(ulClknS * (2 * ((ulDivider / 2) + 1)));

    //
    // Return the divider we calculated.
    //
    return((unsigned short)ulDivider);
}

//*****************************************************************************
//
// Calculate the divider parameter required by EPIDividerSet() based on the
// current system clock rate and the desired EPI rates supplied in the
// usRate0nS and usRate1nS fields of the daughter board information structure.
//
// The dividers are calculated to ensure that the EPI rate is no faster than
// the requested rate and the rate fields in psInfo are updated to reflect the
// actual rate that will be used based on the calculated divider.
//
//*****************************************************************************
static unsigned long
CalcEPIDivider(tDaughterIDInfo *psInfo, unsigned long ulClknS)
{
    unsigned short usDivider0, usDivider1;
    unsigned short usRate0, usRate1;

    //
    // Calculate the dividers required for the two rates specified.
    //
    usRate0 = psInfo->usRate0nS;
    usRate1 = psInfo->usRate1nS;
    usDivider0 = EPIDividerFromRate(&usRate0, ulClknS);
    usDivider1 = EPIDividerFromRate(&usRate1, ulClknS);
    psInfo->usRate0nS = usRate0;
    psInfo->usRate1nS = usRate1;

    //
    // Munge the two dividers together into a format suitable to pass to
    // EPIDividerSet().
    //
    return((unsigned long)usDivider0 | (((unsigned long)usDivider1) << 16));
}

//*****************************************************************************
//
// Returns the configuration parameter for EPIConfigHB8Set() based on the
// config flags and read and write access times found in the psInfo structure,
// and the current EPI clock clock rate as found in the usRate0nS field of the
// psInfo structure.
//
// The EPI clock rate is used to determine the number of wait states required
// so CalcEPIDivider() must have been called before this function to ensure
// that the usRate0nS field has been updated to reflect the actual EPI clock in
// use.  Note, also, that there is only a single read and write wait state
// setting even if dual chip selects are in use.  In this case, the caller
// must ensure that the dividers and access times provided generate suitable
// cycles for the devices attached to both chip selects.
//
//*****************************************************************************
static unsigned long
HB8ConfigGet(tDaughterIDInfo *psInfo)
{
    unsigned long ulConfig, ulWrWait, ulRdWait;

    //
    // Start with the config flags provided in the information structure.
    //
    ulConfig = psInfo->ulConfigFlags;

    //
    // How many write wait states do we need?
    //
    if((unsigned long)psInfo->ucWriteAccTime >
       (EPI_WRITE_CYCLES * (unsigned long)psInfo->usRate0nS))
    {
        //
        // The access time is more than 4 EPI clock cycles so we need to
        // introduce some wait states.  How many?
        //
        ulWrWait = (unsigned long)psInfo->ucWriteAccTime -
                   (EPI_WRITE_CYCLES * psInfo->usRate0nS);
        ulWrWait += ((EPI_WS_CYCLES * psInfo->usRate0nS) - 1);
        ulWrWait /= (EPI_WS_CYCLES * psInfo->usRate0nS);

        //
        // The hardware only allows us to specify 0, 1, 2 or 3 wait states.  If
        // we end up with a number greater than 3, we have a problem.  This
        // indicates an error in the daughter board information structure.
        //
        ASSERT(ulWrWait < 4);

        //
        // Set the configuration flag indicating the desired number of write
        // wait states.
        //
        switch(ulWrWait)
        {
            case 0:
                break;

            case 1:
                ulConfig |= EPI_HB8_WRWAIT_1;
                break;

            case 2:
                ulConfig |= EPI_HB8_WRWAIT_2;
                break;

            case 3:
            default:
                ulConfig |= EPI_HB8_WRWAIT_3;
                break;
        }
    }

    //
    // How many read wait states do we need?
    //
    if((unsigned long)psInfo->ucReadAccTime >
       (EPI_READ_CYCLES * (unsigned long)psInfo->usRate0nS))
    {
        //
        // The access time is more than 3 EPI clock cycles so we need to
        // introduce some wait states.  How many?
        //
        ulRdWait = (unsigned long)psInfo->ucReadAccTime -
                   (EPI_READ_CYCLES * psInfo->usRate0nS);
        ulRdWait += ((EPI_WS_CYCLES * psInfo->usRate0nS) - 1);
        ulRdWait /= (EPI_WS_CYCLES * psInfo->usRate0nS);

        //
        // The hardware only allows us to specify 0, 1, 2 or 3 wait states.  If
        // we end up with a number greater than 3, we have a problem.  This
        // indicates an error in the daughter board information structure.
        //
        ASSERT(ulRdWait < 4);

        //
        // Set the configuration flag indicating the desired number of read
        // wait states.
        //
        switch(ulRdWait)
        {
            case 0:
                break;

            case 1:
                ulConfig |= EPI_HB8_RDWAIT_1;
                break;

            case 2:
                ulConfig |= EPI_HB8_RDWAIT_2;
                break;

            case 3:
            default:
                ulConfig |= EPI_HB8_RDWAIT_3;
                break;
        }
    }

    //
    // Return the configuration flags back to the caller.
    //
    return(ulConfig);
}

//*****************************************************************************
//
// Returns the configuration parameters for EPIConfigSDRAMSet() based on the
// config flags, device size and refresh interval provided in psInfo and the
// system clock rate provided in ulClkHz.
//
//*****************************************************************************
static unsigned long
SDRAMConfigGet(tDaughterIDInfo *psInfo, unsigned long ulClkHz,
               unsigned long *pulRefresh)
{