unsigned long ulConfig;

    //
    // Start with the config flags provided to us.
    //
    ulConfig = psInfo->ulConfigFlags;

    //
    // Set the SDRAM core frequency depending upon the system clock rate.
    //
    if(ulClkHz < 15000000)
    {
        ulConfig |= EPI_SDRAM_CORE_FREQ_0_15;
    }
    else if(ulClkHz < 30000000)
    {
        ulConfig |= EPI_SDRAM_CORE_FREQ_15_30;
    }
    else if(ulClkHz < 50000000)
    {
        ulConfig |= EPI_SDRAM_CORE_FREQ_30_50;
    }
    else
    {
        ulConfig |= EPI_SDRAM_CORE_FREQ_50_100;
    }

    //
    // Now determine the correct refresh count required to refresh the entire
    // device in the time specified.
    //
    *pulRefresh = ((ulClkHz / psInfo->usNumRows) *
                  (unsigned long)psInfo->ucRefreshInterval) / 1000;

    //
    // Return the calculated configuration parameter to the caller.
    //
    return(ulConfig);
}

//*****************************************************************************
//
// Configures all pins associated with the Extended Peripheral Interface (EPI).
//
// \param eDaughter identifies the attached daughter board (if any).
//
// This function configures all pins forming part of the EPI on the device and
// configures the EPI peripheral appropriately for whichever hardware we
// detect is connected to it. On exit, the EPI peripheral is enabled and all
// pins associated with the interface are configured as EPI signals. Drive
// strength is set to 8mA.
//
//*****************************************************************************
static void
EPIPinConfigSet(tDaughterIDInfo *psInfo)
{
    unsigned long ulLoop, ulClk, ulNsPerTick, ulRefresh;
    unsigned char pucPins[NUM_GPIO_PORTS];

    //
    // Enable the EPI peripheral
    //
    SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);

    //
    // Clear our pin bit mask array.
    //
    for(ulLoop = 0; ulLoop < NUM_GPIO_PORTS; ulLoop++)
    {
        pucPins[ulLoop] = 0;
    }

    //
    // Determine the pin bit masks for the EPI pins for each GPIO port.
    //
    for(ulLoop = 0; ulLoop < NUM_EPI_SIGNALS; ulLoop++)
    {
        //
        // Is this EPI signal required?
        //
        if(psInfo->ulEPIPins & (1 << ulLoop))
        {
            //
            // Yes - set the appropriate bit in our pin bit mask array.
            //
            pucPins[g_psEPIPinInfo[ulLoop].ucPortIndex] |=
                (1 << g_psEPIPinInfo[ulLoop].ucPin);
        }
    }

    //
    // At this point, pucPins contains bit masks for each GPIO port with 1s in
    // the positions of every required EPI signal.  Now we need to configure
    // those pins appropriately.  Cycle through each port configuring EPI pins
    // in any port which contains them.
    //
    for(ulLoop = 0; ulLoop < NUM_GPIO_PORTS; ulLoop++)
    {
        //
        // Are there any EPI pins used in this port?
        //
        if(pucPins[ulLoop])
        {
            //
            // Yes - configure the EPI pins.
            //
            GPIOPadConfigSet(g_pulGPIOBase[ulLoop], pucPins[ulLoop],
                             GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
            GPIODirModeSet(g_pulGPIOBase[ulLoop], pucPins[ulLoop],
                           GPIO_DIR_MODE_HW);
        }
    }

    //
    // Now set the EPI operating mode for the daughter board detected.  We need
    // to determine some timing information based on the ID block we have and
    // also the current system clock.
    //
    ulClk = SysCtlClockGet();
    ulNsPerTick = 1000000000/ulClk;

    //
    // If the EPI is not disabled (the daughter board may, for example, want
    // to use all the pins for GPIO), configure the interface as required.
    //
    if(psInfo->ucEPIMode != EPI_MODE_DISABLE)
    {
        //
        // Set the EPI clock divider to ensure a basic EPI clock rate no faster
        // than defined via the ucRate0nS and ucRate1nS fields in the info
        // structure.
        //
        EPIDividerSet(EPI0_BASE, CalcEPIDivider(psInfo, ulNsPerTick));

        //
        // Set the basic EPI operating mode based on the value from the info
        // structure.
        //
        EPIModeSet(EPI0_BASE, psInfo->ucEPIMode);

        //
        // Carry out mode-dependent configuration.
        //
        switch(psInfo->ucEPIMode)
        {
            //
            // The daughter board must be configured for SDRAM operation.
            //
            case EPI_MODE_SDRAM:
            {
                //
                // Work out the SDRAM configuration settings based on the
                // supplied ID structure and system clock rate.
                //
                ulLoop = SDRAMConfigGet(psInfo, ulClk, &ulRefresh);

                //
                // Set the SDRAM configuration.
                //
                EPIConfigSDRAMSet(EPI0_BASE, ulLoop, ulRefresh);
                break;
            }

            //
            // The daughter board must be configured for HostBus8 operation.
            //
            case EPI_MODE_HB8:
            {
                //
                // Determine the number of read and write wait states required
                // to meet the supplied access timing.
                //
                ulLoop = HB8ConfigGet(psInfo);

                //
                // Set the HostBus8 configuration.
                //
                EPIConfigHB8Set(EPI0_BASE, ulLoop, psInfo->ucMaxWait);
                break;
            }

            //
            // The daughter board must be configured for Non-Moded/General
            // Purpose operation.
            //
            case EPI_MODE_GENERAL:
            {
                EPIConfigGPModeSet(EPI0_BASE, psInfo->ulConfigFlags,
                                   psInfo->ucFrameCount, psInfo->ucMaxWait);
                break;
            }
        }

        //
        // Set the EPI address mapping.
        //
        EPIAddressMapSet(EPI0_BASE, psInfo->ucAddrMap);
    }
}

//*****************************************************************************
//
// Set the GPIO port control registers appropriately for the hardware.
//
// This function determines the correct port control settings to enable the
// basic peripheral signals for the dk-lm3s9b96 on their respective pins and
// also ensures that all required EPI signals are correctly routed.  The EPI
// signal configuration is determined from the daughter board information
// structure passed via the \e psInfo parameter.
//
//*****************************************************************************
static void
PortControlSet(tDaughterIDInfo *psInfo)
{
    unsigned long ulPctl[NUM_GPIO_PORTS], ulLoop;

    //
    // To begin with, we set the port control values for all the non-EPI
    // peripherals.
    //

    //
    // GPIO Port A pins
    //
    // To use CAN0, this register value must be changed. The value here
    // enables USB functionality instead of CAN. For CAN, use....
    //
    //  ulPctl[0] = GPIO_PCTL_PA0_U0RX | GPIO_PCTL_PA1_U0TX |
    //              GPIO_PCTL_PA2_SSI0CLK | GPIO_PCTL_PA3_SSI0FSS |
    //              GPIO_PCTL_PA4_SSI0RX | GPIO_PCTL_PA5_SSI0TX |
    //              GPIO_PCTL_PA6_CAN0RX | GPIO_PCTL_PA7_CAN0TX;
    //
    ulPctl[0] = GPIO_PCTL_PA0_U0RX | GPIO_PCTL_PA1_U0TX |
                GPIO_PCTL_PA2_SSI0CLK | GPIO_PCTL_PA3_SSI0FSS |
                GPIO_PCTL_PA4_SSI0RX | GPIO_PCTL_PA5_SSI0TX |
                GPIO_PCTL_PA6_USB0EPEN | GPIO_PCTL_PA7_USB0PFLT;

    //
    // GPIO Port B pins
    //
    ulPctl[1] = GPIO_PCTL_PB2_I2C0SCL | GPIO_PCTL_PB3_I2C0SDA |
                GPIO_PCTL_PB6_I2S0TXSCK | GPIO_PCTL_PB7_NMI;

    //
    // GPIO Port C pins
    //
    ulPctl[2] = GPIO_PCTL_PC0_TCK | GPIO_PCTL_PC1_TMS |
                GPIO_PCTL_PC2_TDI | GPIO_PCTL_PC3_TDO;

    //
    // GPIO Port D pins.
    //
    ulPctl[3] = GPIO_PCTL_PD0_I2S0RXSCK | GPIO_PCTL_PD1_I2S0RXWS |
                GPIO_PCTL_PD4_I2S0RXSD | GPIO_PCTL_PD5_I2S0RXMCLK;

    //
    // GPIO Port E pins
    //
    ulPctl[4] = GPIO_PCTL_PE4_I2S0TXWS | GPIO_PCTL_PE5_I2S0TXSD;

    //
    // GPIO Port F pins
    //
    ulPctl[5] = GPIO_PCTL_PF1_I2S0TXMCLK | GPIO_PCTL_PF2_LED1 |
                GPIO_PCTL_PF3_LED0;

    //
    // GPIO Port G pins
    //
    ulPctl[6] = 0;

    //
    // GPIO Port H pins
    //
    ulPctl[7] = 0;

    //
    // GPIO Port J pins
    //
    ulPctl[8] = 0;

    //
    // Now we OR in the values required for each of the EPI pins depending
    // upon whether or not it is needed.
    //
    for(ulLoop = 0; ulLoop < NUM_EPI_SIGNALS; ulLoop++)
    {
        //
        // Is this EPI pin used by this daughter board?
        //
        if(psInfo->ulEPIPins & (1 << ulLoop))
        {
            //
            // Yes - add the appropriate port control setting for it.
            //
            ulPctl[g_psEPIPinInfo[ulLoop].ucPortIndex] |=
                (g_psEPIPinInfo[ulLoop].ucPctl <<
                 (g_psEPIPinInfo[ulLoop].ucPin * 4));
        }
    }

    //
    // Now that we have determined the required configuration, set the actual
    // port control registers.
    //
    HWREG(GPIO_PORTA_BASE + GPIO_O_PCTL) = ulPctl[0];
    HWREG(GPIO_PORTB_BASE + GPIO_O_PCTL) = ulPctl[1];
    HWREG(GPIO_PORTC_BASE + GPIO_O_PCTL) = ulPctl[2];
    HWREG(GPIO_PORTD_BASE + GPIO_O_PCTL) = ulPctl[3];
    HWREG(GPIO_PORTE_BASE + GPIO_O_PCTL) = ulPctl[4];
    HWREG(GPIO_PORTF_BASE + GPIO_O_PCTL) = ulPctl[5];
    HWREG(GPIO_PORTG_BASE + GPIO_O_PCTL) = ulPctl[6];
    HWREG(GPIO_PORTH_BASE + GPIO_O_PCTL) = ulPctl[7];
    HWREG(GPIO_PORTJ_BASE + GPIO_O_PCTL) = ulPctl[8];
}

//*****************************************************************************
//
//! Configures the LM3S9B96 device pinout for the development board.
//!
//! This function configures each pin of the lm3s9b96 device to route the
//! appropriate peripheral signal as required by the design of the
//! dk-lm3s9b96 development board.
//!
//! \note This module can be built in two ways.  If the label SIMPLE_PINOUT_SET
//! is not defined, the PinoutSet() function will attempt to read an I2C EEPROM
//! to determine which daughter board is attached to the development kit board
//! and use information from that EEPROM to dynamically configure the EPI