?? mfrc500uc.lst
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219 char status = MI_OK;
220
221 FlushFIFO(); // empty FIFO
222 ResetInfo(MInfo);
223 MSndBuffer[0] = 0x10; // addr low byte
224 MSndBuffer[1] = 0x00; // addr high byte
225
226 MSndBuffer[2] = 0x00; // Page
227 MSndBuffer[3] = 0x7B; // RegTxControl modsource 11,InvTx2,Tx2RFEn,TX1RFEn
228 MSndBuffer[4] = 0x3F; // RegCwConductance
229 MSndBuffer[5] = 0x3F; // RFU13
230 MSndBuffer[6] = 0x19; // RFU14
231 MSndBuffer[7] = 0x13; // RegModWidth
232 MSndBuffer[8] = 0x00; // RFU16
233 MSndBuffer[9] = 0x00; // RFU17
234
C51 COMPILER V6.12 MFRC500UC 08/18/2008 15:29:35 PAGE 5
235 MSndBuffer[10] = 0x00; // Page
236 MSndBuffer[11] = 0x73; // RegRxControl1
237 MSndBuffer[12] = 0x08; // RegDecoderControl
238 MSndBuffer[13] = 0x6c; // RegBitPhase
239 MSndBuffer[14] = 0xFF; // RegRxThreshold
240 MSndBuffer[15] = 0x00; // RFU1D
241 MSndBuffer[16] = 0x00; // RegRxControl2
242 MSndBuffer[17] = 0x00; // RegClockQControl
243
244 MSndBuffer[18] = 0x00; // Page
245 MSndBuffer[19] = 0x06; // RegRxWait
246 MSndBuffer[20] = 0x03; // RegChannelRedundancy
247 MSndBuffer[21] = 0x63; // RegCRCPresetLSB
248 MSndBuffer[22] = 0x63; // RegCRCPresetMSB
249 MSndBuffer[23] = 0x0; // RFU25
250 MSndBuffer[24] = 0x04; // RegMfOutSelect enable mfout = manchester HT
251 MSndBuffer[25] = 0x00; // RFU27
252
253 // PAGE 5 FIFO, Timer and IRQ-Pin Configuration
254 MSndBuffer[26] = 0x00; // Page
255 MSndBuffer[27] = 0x08; // RegFIFOLevel
256 MSndBuffer[28] = 0x07; // RegTimerClock
257 MSndBuffer[29] = 0x06; // RegTimerControl
258 MSndBuffer[30] = 0x0A; // RegTimerReload
259 MSndBuffer[31] = 0x02; // RegIRqPinConfig
260 MSndBuffer[32] = 0x00; // RFU
261 MSndBuffer[33] = 0x00; // RFU
262 MInfo.nBytesToSend = 34;
263
264 status = PcdSingleResponseCmd(PCD_WRITEE2,
265 MSndBuffer,
266 MRcvBuffer,
267 &MInfo); // write e2
268 return status;
269 }
270
271 ///////////////////////////////////////////////////////////////////////
272 // M I F A R E R E M O T E A N T E N N A
273 // Configuration of master module
274 ///////////////////////////////////////////////////////////////////////
275 char Mf500ActiveAntennaMasterConfig(void)
276 {
277 char status = MI_OK;
278
279 WriteRC(RegRxControl2,0x42);
280 WriteRC(RegTxControl,0x10);
281 WriteRC(RegBitPhase,0x11);
282
283 return status;
284 }
285
286 ///////////////////////////////////////////////////////////////////////
287 // M I F A R E R E Q U E S T
288 ///////////////////////////////////////////////////////////////////////
289 char Mf500PiccRequest(unsigned char req_code, // request code ALL = 0x52
290 // or IDLE = 0x26
291 unsigned char *atq) // answer to request
292 {
293 return Mf500PiccCommonRequest(req_code,atq);
294 }
295
296 ///////////////////////////////////////////////////////////////////////
C51 COMPILER V6.12 MFRC500UC 08/18/2008 15:29:35 PAGE 6
297 // M I F A R E C O M M O N R E Q U E S T
298 ///////////////////////////////////////////////////////////////////////
299 char Mf500PiccCommonRequest(unsigned char req_code,
300 unsigned char *atq)
301 {
302 char status = MI_OK;
303
304 //************* initialize ******************************
305 if ((status = Mf500PcdSetDefaultAttrib()) == MI_OK)
306 {
307
308 PcdSetTmo(106);
309
310 WriteRC(RegChannelRedundancy,0x03); // RxCRC and TxCRC disable, parity enable
311 ClearBitMask(RegControl,0x08); // disable crypto 1 unit
312 WriteRC(RegBitFraming,0x07); // set TxLastBits to 7
313
314 ResetInfo(MInfo);
315 MSndBuffer[0] = req_code;
316 MInfo.nBytesToSend = 1;
317 status = PcdSingleResponseCmd(PCD_TRANSCEIVE,
318 MSndBuffer,
319 MRcvBuffer,
320 &MInfo);
321
322 if (status) // error occured
323 {
324 *atq = 0;
325 }
326 else
327 {
328 if (MInfo.nBitsReceived != 16) // 2 bytes expected
329 {
330 *atq = 0;
331 status = MI_BITCOUNTERR;
332 }
333 else
334 {
335 status = MI_OK;
336 memcpy(atq,MRcvBuffer,2);
337 }
338 }
339 }
340 return status;
341 }
342
343 ///////////////////////////////////////////////////////////////////////
344 // M I F A R E A N T I C O L L I S I O N
345 // for standard select
346 ///////////////////////////////////////////////////////////////////////
347 char Mf500PiccAnticoll (unsigned char bcnt,
348 unsigned char *snr)
349 {
350 return Mf500PiccCascAnticoll(0x93,bcnt,snr); // first cascade level
351 }
352
353 ///////////////////////////////////////////////////////////////////////
354 // M I F A R E A N T I C O L L I S I O N
355 // for extended serial numbers
356 ///////////////////////////////////////////////////////////////////////
357 char Mf500PiccCascAnticoll (unsigned char select_code,
358 unsigned char bcnt,
C51 COMPILER V6.12 MFRC500UC 08/18/2008 15:29:35 PAGE 7
359 unsigned char *snr)
360 {
361 char status = MI_OK;
362 char snr_in[4]; // copy of the input parameter snr
363 char nbytes = 0; // how many bytes received
364 char nbits = 0; // how many bits received
365 char complete = 0; // complete snr recived
366 char i = 0;
367 char byteOffset = 0;
368 unsigned char snr_crc; // check byte calculation
369 unsigned char snr_check;
370 unsigned char dummyShift1; // dummy byte for snr shift
371 unsigned char dummyShift2; // dummy byte for snr shift
372
373 //************* Initialisierung ******************************
374 if ((status = Mf500PcdSetDefaultAttrib()) == MI_OK)
375 {
376 PcdSetTmo(106);
377
378 memcpy(snr_in,snr,4);
379
380 WriteRC(RegDecoderControl,0x28); // ZeroAfterColl aktivieren
381 ClearBitMask(RegControl,0x08); // disable crypto 1 unit
382
383 //************** Anticollision Loop ***************************
384 complete=0;
385 while (!complete && (status == MI_OK) )
386 {
387 ResetInfo(MInfo);
388 WriteRC(RegChannelRedundancy,0x03); // RxCRC and TxCRC disable, parity enable
389 nbits = bcnt % 8; // remaining number of bits
390 if (nbits)
391 {
392 WriteRC(RegBitFraming,nbits << 4 | nbits); // TxLastBits/RxAlign auf nb_bi
393 nbytes = bcnt / 8 + 1;
394 // number of bytes known
395
396 // in order to solve an inconsistancy in the anticollision sequence
397 // (will be solved soon), the case of 7 bits has to be treated in a
398 // separate way
399 if (nbits == 7 )
400 {
401 MInfo.cmd = PICC_ANTICOLL1; // pass command flag to ISR
402 WriteRC(RegBitFraming,nbits); // reset RxAlign to zero
403 }
404 }
405 else
406 {
407 nbytes = bcnt / 8;
408 }
409
410 MSndBuffer[0] = select_code;
411 MSndBuffer[1] = 0x20 + ((bcnt/8) << 4) + nbits; //number of bytes send
412
413 for (i = 0; i < nbytes; i++) // Sende Buffer beschreiben
414 {
415 MSndBuffer[i + 2] = snr_in[i];
416 }
417 MInfo.nBytesToSend = 2 + nbytes;
418
419 status = PcdSingleResponseCmd(PCD_TRANSCEIVE,
420 MSndBuffer,
C51 COMPILER V6.12 MFRC500UC 08/18/2008 15:29:35 PAGE 8
421 MRcvBuffer,
422 &MInfo);
423
424 // in order to solve an inconsistancy in the anticollision sequence
425 // (will be solved soon), the case of 7 bits has to be treated in a
426 // separate way
427 if (nbits == 7)
428 {
429 // reorder received bits
430 dummyShift1 = 0x00;
431 for (i = 0; i < MInfo.nBytesReceived; i++)
432 {
433 dummyShift2 = MRcvBuffer[i];
434 MRcvBuffer[i] = (dummyShift1 >> (i+1)) | (MRcvBuffer[i] << (7-i));
435 dummyShift1 = dummyShift2;
436 }
437 MInfo.nBitsReceived -= MInfo.nBytesReceived; // subtract received parity bits
438 // recalculation of collision position
439 if ( MInfo.collPos ) MInfo.collPos += 7 - (MInfo.collPos + 6) / 9;
440 }
441
442 if ( status == MI_OK || status == MI_COLLERR) // no other occured
443 {
444 // R e s p o n s e P r o c e s s i n g
445 if ( MInfo.nBitsReceived != (40 - bcnt) ) // not 5 bytes answered
446 {
447 status = MI_BITCOUNTERR;
448 }
449 else
450 {
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