//////////////////////////////////////////////////////////////////////////////
//    Copyright (c), Philips Semiconductors Gratkorn
//
//                     (C)PHILIPS Electronics N.V. 2000
//                          All rights are reserved. 
//  Philips reserves the right to make changes without notice at any time.
// Philips makes no warranty, expressed, implied or statutory, including but
// not limited to any implied warranty of merchantibility or fitness for any
//particular purpose, or that the use will not infringe any third party patent,
// copyright or trademark. Philips must not be liable for any loss or damage
//                          arising from its use.
//////////////////////////////////////////////////////////////////////////////
#ifndef MFRC500REG_H
#define MFRC500REG_H

#ifdef __cplusplus
extern "C"
{
#endif

// PAGE 0      Command and Status
#define     RegPage               0x00   //!< Page Select Register
#define     RegCommand            0x01   //!< Command Register
#define     RegFIFOData           0x02   //!< FiFo Register
#define     RegPrimaryStatus      0x03   //!< Modem State/IRQ/ERR/LoHiAlert Reg
#define     RegFIFOLength         0x04   //!< Buffer length Register
#define     RegSecondaryStatus    0x05   //!< diverse status flags
#define     RegInterruptEn        0x06   //!< IRQ enable Register
#define     RegInterruptRq        0x07   //!< IRQ bits Register
// PAGE 1      Control and Status
#define     RegControl            0x09   //!< processor control
#define     RegErrorFlag          0x0A   /*!< error flags showing the error 
                                         status of the last command executed */
#define     RegCollPos            0x0B   /*!< bit position of the first bit 
                                         collision detected on the 
                                         RF-interface */
#define     RegTimerValue         0x0C   //!< preload value of the timer
#define     RegCRCResultLSB       0x0D   //!< LSB of the CRC Coprocessor register
#define     RegCRCResultMSB       0x0E   //!< MSB of the CRC Coprocessor register
#define     RegBitFraming         0x0F   //!< Adjustments for bit oriented frames
// PAGE 2      Transmitter and Coder Control
#define     RegTxControl          0x11   //!< controls the logical behaviour of 
                                         //!< the antenna driver pins TX1 and TX2
#define     RegCwConductance      0x12   /*!< selects the conductance of the 
                                         antenna driver pins TX1 and TX2 */
#define     RFU13                 0x13   //!< RFU
#define     RegCoderControl       0x14   //!< selects coder rate
#define     RegModWidth           0x15   /*!< selects the width of the 
                                         modulation pulse */
#define     RFU16                 0x16   //!< RFU
#define     RFU17                 0x17   //!< RFU
// PAGE 3      Receiver and Decoder Control
#define     RegRxControl1         0x19   //!< controls receiver behaviour
#define     RegDecoderControl     0x1A   //!< controls decoder behaviour
#define     RegBitPhase           0x1B   /*!< selets the bit phase between 
                                         transmitter and receiver clock */
#define     RegRxThreshold        0x1C   /*!< selects thresholds for the bit 
                                         decoder */
#define     RFU1D                 0x1D   //!< RFU
#define     RegRxControl2         0x1E   /*!< controls decoder behaviour and 
                                         defines the input source for the 
                                         receiver */
#define     RegClockQControl      0x1F   /*!< controls clock generation for the 
                                         90