?? m500auc.lst
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234 // OUT: -
235 // RETURN:
236 // COMMENT: All remaining date in the FIFO of the reader module is
237 // erased by this function. Before wrinting new data or
238 // starting a new command, all remaining data from former
239 // commands should be deleted. Please note, that in
240 // normal operation, never data should be left, that means
C51 COMPILER V6.12 M500AUC 08/23/2008 14:34:32 PAGE 5
241 // that a call to this function should not be necessary.
242 //
243 void FlushFIFO(void);
244
245 // _____________________________________________________________________________
246 //
247 // FUNCTION: M500PiccAuthState
248 // IN: auth_mode
249 // snr
250 // sector
251 // OUT: -
252 // RETURN:
253 // COMMENT:
254 //
255 char M500PiccAuthState(unsigned char auth_mode,// PICC_AUTHENT1A, PICC_AUTHENT1B
256 unsigned char *snr, // 4 byte serial number
257 unsigned char sector); // 0 <= sector <= 15
258 // sector address for authentication
259
260 //////////////////////////////////////////////////////////////////////
261 // EXCHANGE BYTE STREAM
262 ///////////////////////////////////////////////////////////////////////
263 char ExchangeByteStream(unsigned char Cmd,
264 unsigned char *send_data,
265 unsigned char send_bytelen,
266 unsigned char *rec_data,
267 unsigned char *rec_bytelen);
268
269 ///////////////////////////////////////////////////////////////////////////////
270 // Interrupt Handler RC500
271 ///////////////////////////////////////////////////////////////////////////////
272 void RC500ISR (void) interrupt 0 using 1 //Ext0 interrupt
273 {
274 1 static unsigned char idata irqBits;
275 1 static unsigned char idata irqMask;
276 1 static unsigned char idata nbytes;
277 1 static unsigned char idata cnt;
278 1
279 1 IE0 = 0; // Clear interrupt request flag
280 1
281 1 if (MpIsrInfo && MpIsrOut && MpIsrIn) // transfer pointers have to be set
282 1 // correctly
283 1 {
284 2 while( ReadRawIO(RegPrimaryStatus) & 0x08) // loop while IRQ pending
285 2 // Attention: IRQ bit is
286 2 // inverted when used with
287 2 // low activ IRQ
288 2 {
289 3 irqMask = ReadRawIO(RegInterruptEn); // read enabled interrupts
290 3 // read pending interrupts
291 3 irqBits = ReadRawIO(RegInterruptRq) & irqMask;
292 3 MpIsrInfo->irqSource |= irqBits; // save pending interrupts
293 3 //************ LoAlertIRQ ******************
294 3 if (irqBits & 0x01) // LoAlert
295 3 {
296 4 nbytes = MFIFOLength - ReadRawIO(RegFIFOLength);
297 4 // less bytes to send, than space in FIFO
298 4 if ((MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent) <= nbytes)
299 4 {
300 5 nbytes = MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent;
301 5 WriteRawIO(RegInterruptEn,0x01); // disable LoAlert IRQ
302 5 }
C51 COMPILER V6.12 M500AUC 08/23/2008 14:34:32 PAGE 6
303 4 // write remaining data to the FIFO
304 4 for ( cnt = 0;cnt < nbytes;cnt++)
305 4 {
306 5 WriteRawIO(RegFIFOData,MpIsrOut[MpIsrInfo->nBytesSent]);
307 5 MpIsrInfo->nBytesSent++;
308 5 }
309 4 WriteRawIO(RegInterruptRq,0x01); // reset IRQ bit
310 4 }
311 3
312 3 //************* TxIRQ Handling **************
313 3 if (irqBits & 0x10) // TxIRQ
314 3 {
315 4 WriteRawIO(RegInterruptRq,0x10); // reset IRQ bit
316 4 WriteRawIO(RegInterruptEn,0x82); // enable HiAlert Irq for
317 4 // response
318 4 if (MpIsrInfo->cmd == PICC_ANTICOLL1) // if cmd is anticollision
319 4 { // switch off parity generation
320 5 WriteRawIO(RegChannelRedundancy,0x02); // RXCRC and TXCRC disable, parity disable
321 5 }
322 4 }
323 3
324 3 //************* HiAlertIRQ or RxIRQ Handling ******************
325 3 if (irqBits & 0x0E) // HiAlert, Idle or RxIRQ
326 3 {
327 4 // read some bytes ( length of FIFO queue)
328 4 // into the receive buffer
329 4 nbytes = ReadRawIO(RegFIFOLength);
330 4 // read date from the FIFO and store them in the receive buffer
331 4 for ( cnt = 0; cnt < nbytes; cnt++)
332 4 {
333 5 MpIsrIn[MpIsrInfo->nBytesReceived] = ReadRawIO(RegFIFOData);
334 5 MpIsrInfo->nBytesReceived++;
335 5 }
336 4 WriteRawIO(RegInterruptRq,0x0A & irqBits);
337 4 // reset IRQ bit - idle irq will
338 4 // be deleted in a seperate section
339 4 }
340 3
341 3 //************** IdleIRQ Handling ***********
342 3 if (irqBits & 0x04) // Idle IRQ
343 3 {
344 4 WriteRawIO(RegInterruptEn,0x20); // disable Timer IRQ
345 4 WriteRawIO(RegInterruptRq,0x20); // disable Timer IRQ request
346 4 irqBits &= ~0x20; // clear Timer IRQ in local var
347 4 MpIsrInfo->irqSource &= ~0x20; // clear Timer IRQ in info var
348 4 // when idle received, then cancel
349 4 // timeout
350 4 WriteRawIO(RegInterruptRq,0x04); // reset IRQ bit
351 4 // status should still be MI_OK
352 4 // no error - only used for wake up
353 4 }
354 3
355 3 //************* TimerIRQ Handling ***********
356 3 if (irqBits & 0x20) // timer IRQ
357 3 {
358 4 WriteRawIO(RegInterruptRq,0x20); // reset IRQ bit
359 4 MpIsrInfo->status = MI_NOTAGERR; // timeout error
360 4 // otherwise ignore the interrupt
361 4 }
362 3
363 3 }
364 2 }
C51 COMPILER V6.12 M500AUC 08/23/2008 14:34:32 PAGE 7
365 1 }
366
367 ///////////////////////////////////////////////////////////////////////
368 // Set Timeout LENGTH
369 ///////////////////////////////////////////////////////////////////////
370 void M500PcdSetTmo(unsigned char tmoLength)
371 {
372 1 switch(tmoLength)
373 1 { // timer clock frequency 13,56 MHz
374 2 case 1: // short timeout (1,0 ms)
375 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
376 2 WriteIO(RegTimerReload,0x6a);// TReloadVal = 'h6a =106(dec)
377 2 break;
378 2 case 2: // medium timeout (1,5 ms)
379 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
380 2 WriteIO(RegTimerReload,0xa0);// TReloadVal = 'ha0 =160(dec)
381 2 break;
382 2 case 3: // medium timeout (6 ms)
383 2 WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
384 2 WriteIO(RegTimerReload,0xa0);// TReloadVal = 'ha0 =160(dec)
385 2 break;
386 2 case 4: // long timeout (9.6 ms)
387 2 WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
388 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
389 2 break;
390 2 case 5: // long timeout (38.5 ms)
391 2 WriteIO(RegTimerClock,0x0b); // TAutoRestart=0,TPrescale=16*128
392 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
393 2 break;
394 2 case 6: // long timeout (154 ms)
395 2 WriteIO(RegTimerClock,0x0d); // TAutoRestart=0,TPrescale=64*128
396 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
397 2 break;
398 2 case 7: // long timeout (616.2 ms)
399 2 WriteIO(RegTimerClock,0x0f); // TAutoRestart=0,TPrescale=256*128
400 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
401 2 break;
402 2 default: //
403 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
404 2 WriteIO(RegTimerReload,tmoLength);// TReloadVal = 'h6a =tmoLength(dec)
405 2 break;
406 2 }
407 1 }
408
409 //////////////////////////////////////////////////////////////////////
410 // WRITE A PCD COMMAND
411 ///////////////////////////////////////////////////////////////////////
412 char M500PcdCmd(unsigned char cmd,
413 volatile unsigned char* send,
414 volatile unsigned char* rcv,
415 volatile MfCmdInfo *info)
416 {
417 1 char idata status = MI_OK;
418 1 char idata tmpStatus ;
419 1 unsigned char idata lastBits;
420 1
421 1 unsigned char idata irqEn = 0x00;
422 1 unsigned char idata waitFor = 0x00;
423 1 unsigned char idata timerCtl = 0x00;
424 1
425 1 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
426 1 WriteIO(RegInterruptRq,0x7F); // reset interrupt requests
C51 COMPILER V6.12 M500AUC 08/23/2008 14:34:32 PAGE 8
427 1 WriteIO(RegCommand,PCD_IDLE); // terminate probably running command
428 1
429 1 FlushFIFO(); // flush FIFO buffer
430 1
431 1 // save info structures to module pointers
432 1 MpIsrInfo = info;
433 1 MpIsrOut = send;
434 1 MpIsrIn = rcv;
435 1
436 1 info->irqSource = 0x0; // reset interrupt flags
437 1 // depending on the command code, appropriate interrupts are enabled (irqEn)
438 1 // and the commit interrupt is choosen (waitFor).
439 1 switch(cmd)
440 1 {
441 2 case PCD_IDLE: // nothing else required
442 2 irqEn = 0x00;
443 2 waitFor = 0x00;
444 2 break;
445 2 case PCD_WRITEE2: // LoAlert and TxIRq
446 2 irqEn = 0x11;
447 2 waitFor = 0x10;
448 2 break;
449 2 case PCD_READE2: // HiAlert, LoAlert and IdleIRq
450 2 irqEn = 0x07;
451 2 waitFor = 0x04;
452 2 break;
453 2 case PCD_LOADCONFIG: // IdleIRq
454 2 case PCD_LOADKEYE2: // IdleIRq
455 2 case PCD_AUTHENT1: // IdleIRq
456 2 irqEn = 0x05;
457 2 waitFor = 0x04;
458 2 break;
459 2 case PCD_CALCCRC: // LoAlert and TxIRq
460 2 irqEn = 0x11;
461 2 waitFor = 0x10;
462 2 break;
463 2 case PCD_AUTHENT2: // IdleIRq
464 2 irqEn = 0x04;
465 2 waitFor = 0x04;
466 2 break;
467 2 case PCD_RECEIVE: // HiAlert and IdleIRq
468 2 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
469 2 irqEn = 0x06;
470 2 waitFor = 0x04;
471 2 break;
472 2 case PCD_LOADKEY: // IdleIRq
473 2 irqEn = 0x05;
474 2 waitFor = 0x04;
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