/* A DS form instruction.  */#define DSO(op, xop) (OP (op) | ((xop) & 0x3))#define DS_MASK DSO (0x3f, 3)/* An M form instruction.  */#define M(op, rc) (OP (op) | ((rc) & 1))#define M_MASK M (0x3f, 1)/* An M form instruction with the ME field specified.  */#define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1))/* An M_MASK with the MB and ME fields fixed.  */#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)/* An M_MASK with the SH and ME fields fixed.  */#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)/* An MD form instruction.  */#define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1))#define MD_MASK MD (0x3f, 0x7, 1)/* An MD_MASK with the MB field fixed.  */#define MDMB_MASK (MD_MASK | MB6_MASK)/* An MD_MASK with the SH field fixed.  */#define MDSH_MASK (MD_MASK | SH6_MASK)/* An MDS form instruction.  */#define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1))#define MDS_MASK MDS (0x3f, 0xf, 1)/* An MDS_MASK with the MB field fixed.  */#define MDSMB_MASK (MDS_MASK | MB6_MASK)/* An SC form instruction.  */#define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1))#define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1)/* An X form instruction.  */#define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))/* An X form instruction with the RC bit specified.  */#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))/* The mask for an X form instruction.  */#define X_MASK XRC (0x3f, 0x3ff, 1)/* An X_MASK with the RA field fixed.  */#define XRA_MASK (X_MASK | RA_MASK)/* An X_MASK with the RB field fixed.  */#define XRB_MASK (X_MASK | RB_MASK)/* An X_MASK with the RT field fixed.  */#define XRT_MASK (X_MASK | RT_MASK)/* An X_MASK with the RA and RB fields fixed.  */#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)/* An X_MASK with the RT and RA fields fixed.  */#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)/* An X form comparison instruction.  */#define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21))/* The mask for an X form comparison instruction.  */#define XCMP_MASK (X_MASK | (1 << 22))/* The mask for an X form comparison instruction with the L field   fixed.  */#define XCMPL_MASK (XCMP_MASK | (1 << 21))/* An X form trap instruction with the TO field specified.  */#define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21))#define XTO_MASK (X_MASK | TO_MASK)/* An XFL form instruction.  */#define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1))#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16))/* An XL form instruction with the LK field set to 0.  */#define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1))/* An XL form instruction which uses the LK field.  */#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))/* The mask for an XL form instruction.  */#define XL_MASK XLLK (0x3f, 0x3ff, 1)/* An XL form instruction which explicitly sets the BO field.  */#define XLO(op, bo, xop, lk) \  (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21))#define XLO_MASK (XL_MASK | BO_MASK)/* An XL form instruction which explicitly sets the y bit of the BO   field.  */#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21))#define XLYLK_MASK (XL_MASK | Y_MASK)/* An XL form instruction which sets the BO field and the condition   bits of the BI field.  */#define XLOCB(op, bo, cb, xop, lk) \  (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16))#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */#define XLBB_MASK (XL_MASK | BB_MASK)#define XLYBB_MASK (XLYLK_MASK | BB_MASK)#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)/* An XL_MASK with the BO and BB fields fixed.  */#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)/* An XL_MASK with the BO, BI and BB fields fixed.  */#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)/* An XO form instruction.  */#define XO(op, xop, oe, rc) \  (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1))#define XO_MASK XO (0x3f, 0x1ff, 1, 1)/* An XO_MASK with the RB field fixed.  */#define XORB_MASK (XO_MASK | RB_MASK)/* An XS form instruction.  */#define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1))#define XS_MASK XS (0x3f, 0x1ff, 1)/* A mask for the FXM version of an XFX form instruction.  */#define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11))/* An XFX form instruction with the FXM field filled in.  */#define XFXM(op, xop, fxm) \  (X ((op), (xop)) | (((fxm) & 0xff) << 12))/* An XFX form instruction with the SPR field filled in.  */#define XSPR(op, xop, spr) \  (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6))#define XSPR_MASK (X_MASK | SPR_MASK)/* An XFX form instruction with the SPR field filled in except for the   SPRBAT field.  */#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)/* An XFX form instruction with the SPR field filled in except for the   SPRG field.  */#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)/* The BO encodings used in extended conditional branch mnemonics.  */#define BODNZF	(0x0)#define BODNZFP	(0x1)#define BODZF	(0x2)#define BODZFP	(0x3)#define BOF	(0x4)#define BOFP	(0x5)#define BODNZT	(0x8)#define BODNZTP	(0x9)#define BODZT	(0xa)#define BODZTP	(0xb)#define BOT	(0xc)#define BOTP	(0xd)#define BODNZ	(0x10)#define BODNZP	(0x11)#define BODZ	(0x12)#define BODZP	(0x13)#define BOU	(0x14)/* The BI condition bit encodings used in extended conditional branch   mnemonics.  */#define CBLT	(0)#define CBGT	(1)#define CBEQ	(2)#define CBSO	(3)/* The TO encodings used in extended trap mnemonics.  */#define TOLGT	(0x1)#define TOLLT	(0x2)#define TOEQ	(0x4)#define TOLGE	(0x5)#define TOLNL	(0x5)#define TOLLE	(0x6)#define TOLNG	(0x6)#define TOGT	(0x8)#define TOGE	(0xc)#define TONL	(0xc)#define TOLT	(0x10)#define TOLE	(0x14)#define TONG	(0x14)#define TONE	(0x18)#define TOU	(0x1f)/* Smaller names for the flags so each entry in the opcodes table will   fit on a single line.  */#undef PPC#define PPC PPC_OPCODE_PPC#define POWER PPC_OPCODE_POWER#define POWER2 PPC_OPCODE_POWER2#define B32 PPC_OPCODE_32#define B64 PPC_OPCODE_64#define M601 PPC_OPCODE_601/* The opcode table.   The format of the opcode table is:   NAME	     OPCODE	MASK		FLAGS		{ OPERANDS }   NAME is the name of the instruction.   OPCODE is the instruction opcode.   MASK is the opcode mask; this is used to tell the disassembler     which bits in the actual opcode must match OPCODE.   FLAGS are flags indicated what processors support the instruction.   OPERANDS is the list of operands.   The disassembler reads the table in order and prints the first   instruction which matches, so this table is sorted to put more   specific instructions before more general instructions.  It is also   sorted by major opcode.  */const struct powerpc_opcode powerpc_opcodes[] = {{ "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdllti",  OPTO(2,TOLLT), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdllei",  OPTO(2,TOLLE), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdgti",   OPTO(2,TOGT), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdgei",   OPTO(2,TOGE), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdnli",   OPTO(2,TONL), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdlti",   OPTO(2,TOLT), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdlei",   OPTO(2,TOLE), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdngi",   OPTO(2,TONG), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdnei",   OPTO(2,TONE), OPTO_MASK,	PPC|B64,	{ RA, SI } },{ "tdi",     OP(2),	OP_MASK,	PPC|B64,	{ TO, RA, SI } },{ "twlgti",  OPTO(3,TOLGT), OPTO_MASK,	PPC,		{ RA, SI } },{ "tlgti",   OPTO(3,TOLGT), OPTO_MASK,	POWER,		{ RA, SI } },{ "twllti",  OPTO(3,TOLLT), OPTO_MASK,	PPC,		{ RA, SI } },{ "tllti",   OPTO(3,TOLLT), OPTO_MASK,	POWER,		{ RA, SI } },{ "tweqi",   OPTO(3,TOEQ), OPTO_MASK,	PPC,		{ RA, SI } },{ "teqi",    OPTO(3,TOEQ), OPTO_MASK,	POWER,		{ RA, SI } },{ "twlgei",  OPTO(3,TOLGE), OPTO_MASK,	PPC,		{ RA, SI } },{ "tlgei",   OPTO(3,TOLGE), OPTO_MASK,	POWER,		{ RA, SI } },{ "twlnli",  OPTO(3,TOLNL), OPTO_MASK,	PPC,		{ RA, SI } },{ "tlnli",   OPTO(3,TOLNL), OPTO_MASK,	POWER,		{ RA, SI } },{ "twllei",  OPTO(3,TOLLE), OPTO_MASK,	PPC,		{ RA, SI } },{ "tllei",   OPTO(3,TOLLE), OPTO_MASK,	POWER,		{ RA, SI } },{ "twlngi",  OPTO(3,TOLNG), OPTO_MASK,	PPC,		{ RA, SI } },{ "tlngi",   OPTO(3,TOLNG), OPTO_MASK,	POWER,		{ RA, SI } },{ "twgti",   OPTO(3,TOGT), OPTO_MASK,	PPC,		{ RA, SI } },{ "tgti",    OPTO(3,TOGT), OPTO_MASK,	POWER,		{ RA, SI } },{ "twgei",   OPTO(3,TOGE), OPTO_MASK,	PPC,		{ RA, SI } },{ "tgei",    OPTO(3,TOGE), OPTO_MASK,	POWER,		{ RA, SI } },{ "twnli",   OPTO(3,TONL), OPTO_MASK,	PPC,		{ RA, SI } },{ "tnli",    OPTO(3,TONL), OPTO_MASK,	POWER,		{ RA, SI } },{ "twlti",   OPTO(3,TOLT), OPTO_MASK,	PPC,		{ RA, SI } },{ "tlti",    OPTO(3,TOLT), OPTO_MASK,	POWER,		{ RA, SI } },{ "twlei",   OPTO(3,TOLE), OPTO_MASK,	PPC,		{ RA, SI } },{ "tlei",    OPTO(3,TOLE), OPTO_MASK,	POWER,		{ RA, SI } },{ "twngi",   OPTO(3,TONG), OPTO_MASK,	PPC,		{ RA, SI } },{ "tngi",    OPTO(3,TONG), OPTO_MASK,	POWER,		{ RA, SI } },{ "twnei",   OPTO(3,TONE), OPTO_MASK,	PPC,		{ RA, SI } },{ "tnei",    OPTO(3,TONE), OPTO_MASK,	POWER,		{ RA, SI } },{ "twi",     OP(3),	OP_MASK,	PPC,		{ TO, RA, SI } },{ "ti",      OP(3),	OP_MASK,	POWER,		{ TO, RA, SI } },{ "mulli",   OP(7),	OP_MASK,	PPC,		{ RT, RA, SI } },{ "muli",    OP(7),	OP_MASK,	POWER,		{ RT, RA, SI } },{ "subfic",  OP(8),	OP_MASK,	PPC,		{ RT, RA, SI } },{ "sfi",     OP(8),	OP_MASK,	POWER,		{ RT, RA, SI } },{ "dozi",    OP(9),	OP_MASK,	POWER|M601,	{ RT, RA, SI } },{ "cmplwi",  OPL(10,0),	OPL_MASK,	PPC,		{ OBF, RA, UI } },{ "cmpldi",  OPL(10,1), OPL_MASK,	PPC|B64,	{ OBF, RA, UI } },{ "cmpli",   OP(10),	OP_MASK,	PPC,		{ BF, L, RA, UI } },{ "cmpli",   OP(10),	OP_MASK,	POWER,		{ BF, RA, UI } },{ "cmpwi",   OPL(11,0),	OPL_MASK,	PPC,		{ OBF, RA, SI } },{ "cmpdi",   OPL(11,1),	OPL_MASK,	PPC|B64,	{ OBF, RA, SI } },{ "cmpi",    OP(11),	OP_MASK,	PPC,		{ BF, L, RA, SI } },{ "cmpi",    OP(11),	OP_MASK,	POWER,		{ BF, RA, SI } },{ "addic",   OP(12),	OP_MASK,	PPC,		{ RT, RA, SI } },{ "ai",	     OP(12),	OP_MASK,	POWER,		{ RT, RA, SI } },{ "subic",   OP(12),	OP_MASK,	PPC,		{ RT, RA, NSI } },{ "addic.",  OP(13),	OP_MASK,	PPC,		{ RT, RA, SI } },{ "ai.",     OP(13),	OP_MASK,	POWER,		{ RT, RA, SI } },{ "subic.",  OP(13),	OP_MASK,	PPC,		{ RT, RA, NSI } },{ "li",	     OP(14),	DRA_MASK,	PPC,		{ RT, SI } },{ "lil",     OP(14),	DRA_MASK,	POWER,		{ RT, SI } },{ "addi",    OP(14),	OP_MASK,	PPC,		{ RT, RA, SI } },{ "cal",     OP(14),	OP_MASK,	POWER,		{ RT, D, RA } },{ "subi",    OP(14),	OP_MASK,	PPC,		{ RT, RA, NSI } },{ "la",	     OP(14),	OP_MASK,	PPC,		{ RT, D, RA } },{ "lis",     OP(15),	DRA_MASK,	PPC,		{ RT, SISIGNOPT } },{ "liu",     OP(15),	DRA_MASK,	POWER,		{ RT, SISIGNOPT } },{ "addis",   OP(15),	OP_MASK,	PPC,		{ RT,RA,SISIGNOPT } },{ "cau",     OP(15),	OP_MASK,	POWER,		{ RT,RA,SISIGNOPT } },{ "subis",   OP(15),	OP_MASK,	PPC,		{ RT, RA, NSI } },{ "bdnz-",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC,	{ BDM } },{ "bdnz+",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC,	{ BDP } },{ "bdnz",    BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC,	{ BD } },{ "bdn",     BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER,	{ BD } },{ "bdnzl-",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC,	{ BDM } },{ "bdnzl+",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC,	{ BDP } },{ "bdnzl",   BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC,	{ BD } },{ "bdnl",    BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER,	{ BD } },{ "bdnza-",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC,	{ BDMA } },{ "bdnza+",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC,	{ BDPA } },{ "bdnza",   BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC,	{ BDA } },{ "bdna",    BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER,	{ BDA } },{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC,	{ BDMA } },{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC,	{ BDPA } },{ "bdnzla",  BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC,	{ BDA } },{ "bdnla",   BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER,	{ BDA } },{ "bdz-",    BBO(16,BODZ,0,0), BBOYBI_MASK, PPC,	{ BDM } },{ "bdz+",    BBO(16,BODZ,0,0), BBOYBI_MASK, PPC,	{ BDP } },{ "bdz",     BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER,	{ BD } },{ "bdzl-",   BBO(16,BODZ,0,1), BBOYBI_MASK, PPC,	{ BDM } },{ "bdzl+",   BBO(16,BODZ,0,1), BBOYBI_MASK, PPC,	{ BDP } },{ "bdzl",    BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER,	{ BD } },{ "bdza-",   BBO(16,BODZ,1,0), BBOYBI_MASK, PPC,	{ BDMA } },{ "bdza+",   BBO(16,BODZ,1,0), BBOYBI_MASK, PPC,	{ BDPA } },{ "bdza",    BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER,	{ BDA } },{ "bdzla-",  BBO(16,BODZ,1,1), BBOYBI_MASK, PPC,	{ BDMA } },{ "bdzla+",  BBO(16,BODZ,1,1), BBOYBI_MASK, PPC,	{ BDPA } },{ "bdzla",   BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER,	{ BDA } },{ "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC,	{ CR, BDM } },{ "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC,	{ CR, BDP } },{ "blt",     BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } },{ "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC,	{ CR, BDM } },{ "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC,	{ CR, BDP } },{ "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } },{ "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC,	{ CR, BDMA } },{ "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC,	{ CR, BDPA } },{ "blta",    BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } },