?? do.i
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#line 1 "do.c" /0 #line 1 "c8051f040.h" /0 sfr P0 = 0x80; sfr SP = 0x81; sfr DPL = 0x82; sfr DPH = 0x83; sfr SFRPAGE = 0x84; sfr SFRNEXT = 0x85; sfr SFRLAST = 0x86; sfr PCON = 0x87; sfr TCON = 0x88; sfr CPT0CN = 0x88; sfr CPT1CN = 0x88; sfr CPT2CN = 0x88; sfr TMOD = 0x89; sfr CPT0MD = 0x89; sfr CPT1MD = 0x89; sfr CPT2MD = 0x89; sfr TL0 = 0x8A; sfr OSCICN = 0x8A; sfr TL1 = 0x8B; sfr OSCICL = 0x8B; sfr TH0 = 0x8C; sfr OSCXCN = 0x8C; sfr TH1 = 0x8D; sfr CKCON = 0x8E; sfr PSCTL = 0x8F; sfr P1 = 0x90; sfr SSTA0 = 0x91; sfr SFRPGCN = 0x96; sfr CLKSEL = 0x97; sfr SCON0 = 0x98; sfr SCON1 = 0x98; sfr SBUF0 = 0x99; sfr SBUF1 = 0x99; sfr SPI0CFG = 0x9A; sfr SPI0DAT = 0x9B; sfr P4MDOUT = 0x9C; sfr SPI0CKR = 0x9D; sfr P5MDOUT = 0x9D; sfr P6MDOUT = 0x9E; sfr P7MDOUT = 0x9F; sfr P2 = 0xA0; sfr EMI0TC = 0xA1; sfr EMI0CN = 0xA2; sfr EMI0CF = 0xA3; sfr P0MDOUT = 0xA4; sfr P1MDOUT = 0xA5; sfr P2MDOUT = 0xA6; sfr P3MDOUT = 0xA7; sfr IE = 0xA8; sfr SADDR0 = 0xA9; sfr SADDR1 = 0xA9; sfr P1MDIN = 0xAD; sfr P2MDIN = 0xAE; sfr P3MDIN = 0xAF; sfr P3 = 0xB0; sfr FLSCL = 0xB7; sfr FLACL = 0xB7; sfr IP = 0xB8; sfr SADEN0 = 0xB9; sfr AMX2CF = 0xBA; sfr AMX0PRT = 0xBD; sfr AMX0CF = 0xBA; sfr AMX0SL = 0xBB; sfr AMX2SL = 0xBB; sfr ADC0CF = 0xBC; sfr ADC2CF = 0xBC; sfr ADC0L = 0xBE; sfr ADC2 = 0xBE; sfr ADC0H = 0xBF; sfr SMB0CN = 0xC0; sfr CAN0STA = 0xC0; sfr SMB0STA = 0xC1; sfr SMB0DAT = 0xC2; sfr SMB0ADR = 0xC3; sfr ADC0GTL = 0xC4; sfr ADC2GT = 0xC4; sfr ADC0GTH = 0xC5; sfr ADC0LTL = 0xC6; sfr ADC2LT = 0xC6; sfr ADC0LTH = 0xC7; sfr TMR2CN = 0xC8; sfr TMR3CN = 0xC8; sfr TMR4CN = 0xC8; sfr P4 = 0xC8; sfr TMR2CF = 0xC9; sfr TMR3CF = 0xC9; sfr TMR4CF = 0xC9; sfr RCAP2L = 0xCA; sfr RCAP3L = 0xCA; sfr RCAP4L = 0xCA; sfr RCAP2H = 0xCB; sfr RCAP3H = 0xCB; sfr RCAP4H = 0xCB; sfr TMR2L = 0xCC; sfr TMR3L = 0xCC; sfr TMR4L = 0xCC; sfr TMR2H = 0xCD; sfr TMR3H = 0xCD; sfr TMR4H = 0xCD; sfr SMB0CR = 0xCF; sfr PSW = 0xD0; sfr REF0CN = 0xD1; sfr DAC0L = 0xD2; sfr DAC1L = 0xD2; sfr DAC0H = 0xD3; sfr DAC1H = 0xD3; sfr DAC0CN = 0xD4; sfr DAC1CN = 0xD4; sfr HVA0CN = 0xD6; sfr PCA0CN = 0xD8; sfr CAN0DATL = 0xD8; sfr P5 = 0xD8; sfr PCA0MD = 0xD9; sfr CAN0DATH = 0xD9; sfr PCA0CPM0 = 0xDA; sfr CAN0ADR = 0xDA; sfr PCA0CPM1 = 0xDB; sfr CAN0TST = 0xDB; sfr PCA0CPM2 = 0xDC; sfr PCA0CPM3 = 0xDD; sfr PCA0CPM4 = 0xDE; sfr PCA0CPM5 = 0xDF; sfr ACC = 0xE0; sfr PCA0CPL5 = 0xE1; sfr XBR0 = 0xE1; sfr PCA0CPH5 = 0xE2; sfr XBR1 = 0xE2; sfr XBR2 = 0xE3; sfr XBR3 = 0xE4; sfr EIE1 = 0xE6; sfr EIE2 = 0xE7; sfr ADC0CN = 0xE8; sfr ADC2CN = 0xE8; sfr P6 = 0xE8; sfr PCA0CPL2 = 0xE9; sfr PCA0CPH2 = 0xEA; sfr PCA0CPL3 = 0xEB; sfr PCA0CPH3 = 0xEC; sfr PCA0CPL4 = 0xED; sfr PCA0CPH4 = 0xEE; sfr RSTSRC = 0xEF; sfr B = 0xF0; sfr EIP1 = 0xF6; sfr EIP2 = 0xF7; sfr SPI0CN = 0xF8; sfr CAN0CN = 0xF8; sfr P7 = 0xF8; sfr PCA0L = 0xF9; sfr PCA0H = 0xFA; sfr PCA0CPL0 = 0xFB; sfr PCA0CPH0 = 0xFC; sfr PCA0CPL1 = 0xFD; sfr PCA0CPH1 = 0xFE; sfr WDTCN = 0xFF; sbit TF1 = TCON ^ 7; sbit TR1 = TCON ^ 6; sbit TF0 = TCON ^ 5; sbit TR0 = TCON ^ 4; sbit IE1 = TCON ^ 3; sbit IT1 = TCON ^ 2; sbit IE0 = TCON ^ 1; sbit IT0 = TCON ^ 0; sbit CP0EN = CPT0CN ^ 7; sbit CP0OUT = CPT0CN ^ 6; sbit CP0RIF = CPT0CN ^ 5; sbit CP0FIF = CPT0CN ^ 4; sbit CP0HYP1 = CPT0CN ^ 3; sbit CP0HYP0 = CPT0CN ^ 2; sbit CP0HYN1 = CPT0CN ^ 1; sbit CP0HYN0 = CPT0CN ^ 0; sbit CP1EN = CPT1CN ^ 7; sbit CP1OUT = CPT1CN ^ 6; sbit CP1RIF = CPT1CN ^ 5; sbit CP1FIF = CPT1CN ^ 4; sbit CP1HYP1 = CPT1CN ^ 3; sbit CP1HYP0 = CPT1CN ^ 2; sbit CP1HYN1 = CPT1CN ^ 1; sbit CP1HYN0 = CPT1CN ^ 0; sbit CP2EN = CPT2CN ^ 7; sbit CP2OUT = CPT2CN ^ 6; sbit CP2RIF = CPT2CN ^ 5; sbit CP2FIF = CPT2CN ^ 4; sbit CP2HYP1 = CPT2CN ^ 3; sbit CP2HYP0 = CPT2CN ^ 2; sbit CP2HYN1 = CPT2CN ^ 1; sbit CP2HYN0 = CPT2CN ^ 0; sbit SM00 = SCON0 ^ 7; sbit SM10 = SCON0 ^ 6; sbit SM20 = SCON0 ^ 5; sbit REN0 = SCON0 ^ 4; sbit TB80 = SCON0 ^ 3; sbit RB80 = SCON0 ^ 2; sbit TI0 = SCON0 ^ 1; sbit RI0 = SCON0 ^ 0; sbit S0MODE = SCON1 ^ 7; sbit MCE1 = SCON1 ^ 5; sbit REN1 = SCON1 ^ 4; sbit TB81 = SCON1 ^ 3; sbit RB81 = SCON1 ^ 2; sbit TI1 = SCON1 ^ 1; sbit RI1 = SCON1 ^ 0; sbit EA = IE ^ 7; sbit ET2 = IE ^ 5; sbit ES0 = IE ^ 4; sbit ET1 = IE ^ 3; sbit EX1 = IE ^ 2; sbit ET0 = IE ^ 1; sbit EX0 = IE ^ 0; sbit PT2 = IP ^ 5; sbit PS = IP ^ 4; sbit PT1 = IP ^ 3; sbit PX1 = IP ^ 2; sbit PT0 = IP ^ 1; sbit PX0 = IP ^ 0; sbit BUSY = SMB0CN ^ 7; sbit ENSMB = SMB0CN ^ 6; sbit STA = SMB0CN ^ 5; sbit STO = SMB0CN ^ 4; sbit SI = SMB0CN ^ 3; sbit AA = SMB0CN ^ 2; sbit SMBFTE = SMB0CN ^ 1; sbit SMBTOE = SMB0CN ^ 0; sbit BOFF = CAN0STA ^ 7; sbit EWARN = CAN0STA ^ 6; sbit EPASS = CAN0STA ^ 5; sbit RXOK = CAN0STA ^ 4; sbit TXOK = CAN0STA ^ 3; sbit LEC2 = CAN0STA ^ 2; sbit LEC1 = CAN0STA ^ 1; sbit LEC0 = CAN0STA ^ 0; sbit TF2 = TMR2CN ^ 7; sbit EXF2 = TMR2CN ^ 6; sbit EXEN2 = TMR2CN ^ 3; sbit TR2 = TMR2CN ^ 2; sbit CT2 = TMR2CN ^ 1; sbit CPRL2 = TMR2CN ^ 0; sbit TF3 = TMR3CN ^ 7; sbit EXF3 = TMR3CN ^ 6; sbit EXEN3 = TMR3CN ^ 3; sbit TR3 = TMR3CN ^ 2; sbit CT3 = TMR3CN ^ 1; sbit CPRL3 = TMR3CN ^ 0; sbit TF4 = TMR4CN ^ 7; sbit EXF4 = TMR4CN ^ 6; sbit EXEN4 = TMR4CN ^ 3; sbit TR4 = TMR4CN ^ 2; sbit CT4 = TMR4CN ^ 1; sbit CPRL4 = TMR4CN ^ 0; sbit CY = PSW ^ 7; sbit AC = PSW ^ 6; sbit F0 = PSW ^ 5; sbit RS1 = PSW ^ 4; sbit RS0 = PSW ^ 3; sbit OV = PSW ^ 2; sbit F1 = PSW ^ 1; sbit P = PSW ^ 0; sbit CF = PCA0CN ^ 7; sbit CR = PCA0CN ^ 6; sbit CCF5 = PCA0CN ^ 5; sbit CCF4 = PCA0CN ^ 4; sbit CCF3 = PCA0CN ^ 3; sbit CCF2 = PCA0CN ^ 2; sbit CCF1 = PCA0CN ^ 1; sbit CCF0 = PCA0CN ^ 0; sbit AD0EN = ADC0CN ^ 7; sbit AD0TM = ADC0CN ^ 6; sbit AD0INT = ADC0CN ^ 5; sbit AD0BUSY = ADC0CN ^ 4; sbit AD0CM1 = ADC0CN ^ 3; sbit AD0CM0 = ADC0CN ^ 2; sbit AD0WINT = ADC0CN ^ 1; sbit AD2EN = ADC2CN ^ 7; sbit AD2TM = ADC2CN ^ 6; sbit AD2INT = ADC2CN ^ 5; sbit AD2BUSY = ADC2CN ^ 4; sbit AD2WINT = ADC2CN ^ 3; sbit AD2CM2 = ADC2CN ^ 2; sbit AD2CM1 = ADC2CN ^ 1; sbit AD2CM0 = ADC2CN ^ 0; sbit SPIF = SPI0CN ^ 7; sbit WCOL = SPI0CN ^ 6; sbit MODF = SPI0CN ^ 5; sbit RXOVRN = SPI0CN ^ 4; sbit NSSMD1 = SPI0CN ^ 3; sbit NSSMD0 = SPI0CN ^ 2; sbit TXBMT = SPI0CN ^ 1; sbit SPIEN = SPI0CN ^ 0; sbit CANINIT = CAN0CN ^ 0; sbit CANIE = CAN0CN ^ 1; sbit CANSIE = CAN0CN ^ 2; sbit CANEIE = CAN0CN ^ 3; sbit CANIF = CAN0CN ^ 4; sbit CANDAR = CAN0CN ^ 5; sbit CANCCE = CAN0CN ^ 6; sbit CANTEST = CAN0CN ^ 7; #line 1 "do.c" /0 #line 1 "can.h" /0 #line 2 "do.c" /0 void SYSCLK_Init (void); void PORT_Init (void); void INT_Init (void); void CAN_Init (void); void CAN_Transmit_Init (void); void CAN_Receive_Init (void); void Timer_Init (void); void CAN_Receive_Interrupt (void); void INT0_Interrupt (void); void Timer0_Overflow_Interrupt (void); void Control_DO (void); sbit OE = P4^0; sbit CANLED = P4^1; bit DO_Error_Flag; bit DO_Control_Flag; bit DO_Message_Req_Flag; unsigned char DO_Address; unsigned char DO_Control_Data0; unsigned char DO_Control_Data1; unsigned char DO_Control_Data_New0; unsigned char DO_Control_Data_New1; unsigned char DO_Control_Data_Ordered0; unsigned char DO_Control_Data_Ordered1; unsigned char DO_Error_Data; unsigned char DO_Error_Filter_Counter; unsigned char CANLED_Counter; unsigned int Counter_For_DO_Error; void main () { EA = 0; WDTCN = 0xDE; WDTCN = 0xAD; SYSCLK_Init (); PORT_Init (); INT_Init (); CAN_Init (); CAN_Transmit_Init (); CAN_Receive_Init (); Timer_Init (); OE = 0; EA = 1; TR0 = 1; while (1) { if (DO_Control_Flag == 1) { Control_DO (); } } } void CAN_Receive_Interrupt (void) interrupt 19 { unsigned char temp1, temp2; SFRPAGE = 0x01; CAN0ADR = 0x21; CAN0DATL = 0x7F; CAN0ADR = 0x20; CAN0DATL = 0x02; CAN0ADR = 0x27; temp1 = CAN0DATH; temp2 = CAN0DATL; DO_Control_Data_New0 = CAN0DATH; DO_Control_Data_New1 = CAN0DATL; if (((temp2 == (0x10 | 0x01 )) && (temp1 == 0x0F))) { DO_Control_Flag = 1; } CANLED_Counter = CANLED_Counter + 1; if (CANLED_Counter == 30){ SFRPAGE = 0x0F; CANLED = ~CANLED; CANLED_Counter = 0; } SFRPAGE = 0x00; TR0 = 0; TH0 = 0xFF; TL0 = 0xFF; TR0 = 1; Counter_For_DO_Error = 0; } void Control_DO (void) { unsigned char PAGE_TEMP; PAGE_TEMP = SFRPAGE; SFRPAGE = 0x0F; DO_Control_Data0 = DO_Control_Data_New0; DO_Control_Data1 = DO_Control_Data_New1; DO_Control_Flag = 0; EA = 0; P5 = DO_Control_Data0; P6 = DO_Control_Data1; EA = 1; SFRPAGE = PAGE_TEMP; } void Timer0_Overflow_Interrupt (void) interrupt 1 { Counter_For_DO_Error++; if (Counter_For_DO_Error == 0xFFFF) { SFRPAGE = 0xF; P5 = 0xFF; P6 = 0xFF; Counter_For_DO_Error = 0; } SFRPAGE = 0x00; TR0 = 0; TH0 = 0xFF; TL0 = 0xFF; TR0 = 1; }?? 快捷鍵說明
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