#include"PXA255.h"
#include"RC531.h"
#include"PICC.h"

//#define READER_INT_ENABLE     


#define TCLFSDSNDMAX   8   ///< max. frame size send
#define TCLFSDRECMAX   8   ///< max. frame size rcv
#define TCLDSMAX       3   ///< max. baudrate divider PICC --> PCD
#define TCLDRMAX       3   ///< max. baudrate divider PCD --> PICC

#define TCLDSDFLT      0   ///< default baudrate divider PICC --> PCD
#define TCLDRDFLT      0   ///< default baudrate divider PCD --> PICC
// data send baudrate divider PICC --> PCD
static U8 MDSI = TCLDSDFLT;    

// data send baudrate divider PCD --> PICC
static U8 MDRI = TCLDRDFLT;   
typedef struct 
         {
            unsigned short  SubCarrierPulses; ///< RegRxControl1
            unsigned short  RxCoding;         ///< RegDecoderControl
            unsigned short  RxThreshold;      ///< RegRxThreshold
            unsigned short  BPSKDemControl;   ///< RegBPSKDemControl
         } t_DSCfg;

typedef struct 
         {
            unsigned short  CoderRate;        ///< RegCoderControl
            unsigned short  ModWidth;         ///< RegModWidth
         } t_DRCfg;

const t_DSCfg  MDSCfg[4] = {{0x73,0x08,0x88,0x00}     	// Manchaster 106 kBaud
                            ,{0x53,0x09,0x50,0x0C}     	// BPSK 212 kBaud
                            ,{0x33,0x09,0x50,0x0C}     	// BPSK 424 kBaud
                            ,{0x13,0x09,0x50,0x0C}};   	// BPSK 848 kBaud
const t_DRCfg  MDRCfg[4] = {{0x19,0x13}          		// Miller 106 kBaud
                            ,{0x11,0x07}          		// Miller 212 kBaud
                            ,{0x09,0x03}          		// Miller 424 kBaud
                            ,{0x01,0x01}};        		// Miller 848 kBaud
                            
typedef struct 
         {
            unsigned char  cmd;           //!< command code 
            char           status;        //!< communication status
            unsigned short nBytesSent;    //!< how many bytes already sent
            unsigned short nBytesToSend;  //!< how many bytes to send
            unsigned short nBytesReceived;//!< how many bytes received
            unsigned long  nBitsReceived; //!< how many bits received
            unsigned char  irqSource;     //!< which interrupts have occured
            unsigned char  collPos;       /*!< at which position occured a
                                          collision*/
            unsigned char  errFlags;      //!< error flags
            unsigned char  saveErrorState;//!< accumulated error flags for
                                          //!< multiple responses
            unsigned char  RxAlignWA;     //!< workaround for RxAlign = 7
            unsigned char  DisableDF;     //!< disable disturbance filter
         } MfCmdInfo;

// Convinience function for initialising the communication structure.
#define ResetInfo(info)    \
            info.cmd            = 0; \
            info.status         = MI_OK;\
            info.irqSource      = 0; \
            info.nBytesSent     = 0; \
            info.nBytesToSend   = 0; \
            info.nBytesReceived = 0; \
            info.nBitsReceived  = 0; \
            info.collPos        = 0; \
            info.errFlags       = 0; \
            info.saveErrorState = 0; \
            info.RxAlignWA      = 0; \
            info.DisableDF      = 0;

// In order to exchange some values between the ISR and the calling function,
// a struct is provided. 
volatile MfCmdInfo     MInfo;   
static   volatile MfCmdInfo     *MpIsrInfo = 0;                            
static   volatile unsigned char *MpIsrOut = 0; 
// ISR receive buffer
static   volatile unsigned char *MpIsrIn = 0;   

                            
volatile U8 MemPool[300];

volatile U8 *MSndBuffer = MemPool; // pointer to the transmit buffer
volatile U8 *MRcvBuffer = MemPool; // pointer to the receive buffer                        
                            
                            
void Write_RF531(U8 addr,U8 dat)
{
	Write_RE(0x00,((addr>>3)|0x80));			//set page
	Write_RE((addr&0x07),dat);
}
U8 Read_RF531(U8 addr)
{
	U8 i;
	Write_RE(0x00,((addr>>3)|0x80));			//set page
	i=Read_RE((addr&0x07));
	return i;
	
}

U8 PCD_Reset(void)
{
	
	RF531_RESET
	Delay_us(10);
	RF531_CLEAR_RESET
   	while (((Read_RF531(RegCommand) & 0x3F) != 0x3F));
	while ((Read_RF531(RegCommand) & 0x3F));
   	Write_RF531(RegPage,0x80);					 // Dummy access in order to determine the bus 
   	if (Read_RF531(RegCommand) != 0x00)
		return 0;
	return 1;
}

void SetBitMask(U8 reg,U8 mask)
{
   U8  tmp    = 0x0;
   tmp =Read_RF531(reg);
   Write_RF531(reg,tmp | mask);  				// set bit mask
}

//////////////////////////////////////////////////////////////////////
//   C L E A R   A   B I T   M A S K 
///////////////////////////////////////////////////////////////////////
void ClearBitMask(U8 reg,U8 mask) 
{
   U8   tmp    = 0x0;
   tmp = Read_RF531(reg);
   Write_RF531(reg,tmp & ~mask);  				// clear bit mask
}

void FlushFIFO(void)
{  
   SetBitMask(RegControl,0x01);
}

void PcdRfReset(U8 ms)
{	
   ClearBitMask(RegTxControl,0x03); 			// Tx2RF-En, Tx1RF-En disablen
   if (ms > 0)
   {
      Delay_us(ms*1000);                      	// Delay for 1 ms 
      SetBitMask(RegTxControl,0x03);    		// Tx2RF-En, Tx1RF-En enable
   }
}

void PcdBasicRegisterConfiguration(void)
{
  												// test clock Q calibration - value in the range of 0x46 expected
  Write_RF531(RegClockQControl,0x0);
  Write_RF531(RegClockQControl,0x40);
  Delay_us(100);  								// wait approximately 100 us - calibration in progress
  ClearBitMask(RegClockQControl,0x40); 			// clear bit ClkQCalib for further calibration  enable auto power down
  Write_RF531(RegRxControl2,0x41);
  Write_RF531(RegIRqPinConfig,0x3); 			// interrupt active low enable
} 

void Mf500PcdWriteAttrib(void)
{    											// adjust baudrate and pauselength of reader
    Write_RF531(RegBPSKDemControl,0x0e);   		// RegBPSKDemControl  
    											// set reader send baudrate
    Write_RF531(RegCoderControl,MDRCfg[MDRI].CoderRate);
    Write_RF531(RegModWidth,MDRCfg[MDRI].ModWidth);   
    											// set reader receive baudrate
    Write_RF531(RegRxControl1,MDSCfg[MDSI].SubCarrierPulses);		//0x73
    Write_RF531(RegDecoderControl,MDSCfg[MDSI].RxCoding);      
    Write_RF531(RegRxThreshold,MDSCfg[MDSI].RxThreshold);
    Write_RF531(RegBPSKDemControl,MDSCfg[MDSI].BPSKDemControl);
}

void Mf500PcdConfig(void)
{
    PCD_Reset();
    PcdBasicRegisterConfiguration();
    Mf500PcdWriteAttrib(); 						// write current modulation parameters
    PcdRfReset(1); 								// Rf - reset and enable output driver    
}

///////////////////////////////////////////////////////////////////////
//          M I F A R E   R E M O T E   A N T E N N A
//  Configuration of master module
///////////////////////////////////////////////////////////////////////
void Mf500ActiveAntennaMasterConfig(void)
{
   	Write_RF531(RegRxControl2,0x42);
   	Write_RF531(RegTxControl,0x10);
   	Write_RF531(RegBitPhase,0x11);
  	Write_RF531(RegMfOutSelect,0x02);
}     

U8 Mf500PcdSetAttrib(U8 DSI, U8 DRI)
{ 
  	if ( ( DSI > TCLDSMAX ) || ( DRI > TCLDRMAX ) ) // Return error, if adjusted baudrate not supported by PCD
  	{
    	return 0 ;
  	}else{
   	 	MDSI = DSI;
    	MDRI = DRI;
    	Mf500PcdWriteAttrib();
  	}
  	return 1;
}

U8 Mf500PcdSetDefaultAttrib(void)
{
   	U8  status;
   	// switch to 106 kBaud (default)
   	// if last reader receive baud rate is different to the default value
   	// or last reader send baud rate is different to the default value
   	if ((MDSI != TCLDSDFLT) || (MDRI != TCLDRDFLT))
   	{
      	status = Mf500PcdSetAttrib(TCLDSDFLT,TCLDRDFLT);
   	}
   	return status;
}

U8 PcdSetTmo(U16 tmoLength)
{
    U8 prescale = 7;
    U16 reload = tmoLength;
    while (reload > 255)
    {
       prescale++;
       reload = reload >> 1; // division by 2
    }
    // if one of the higher bits are set, the prescaler is set
    // to the largest value
    if (prescale > 0x15)				// fcnt = 13560000 / (2^prescale)
    {