?? psp.pin
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-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (2.5V/3.3V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
CHIP "PSP" ASSIGNED TO AN: EPM570T144C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
VS : 1 : output : 3.3-V LVTTL : : 1 : Y
HS : 2 : output : 3.3-V LVTTL : : 1 : Y
DISP : 3 : output : 3.3-V LVTTL : : 1 : Y
pspclk : 4 : output : 3.3-V LVTTL : : 1 : Y
pspdata[7] : 5 : output : 3.3-V LVTTL : : 1 : Y
pspdata[6] : 6 : output : 3.3-V LVTTL : : 1 : Y
pspdata[5] : 7 : output : 3.3-V LVTTL : : 1 : Y
pspdata[4] : 8 : output : 3.3-V LVTTL : : 1 : Y
VCCIO1 : 9 : power : : 3.3V : 1 :
GNDIO : 10 : gnd : : : :
pspdata[3] : 11 : output : 3.3-V LVTTL : : 1 : Y
pspdata[2] : 12 : output : 3.3-V LVTTL : : 1 : Y
pspdata[1] : 13 : output : 3.3-V LVTTL : : 1 : Y
pspdata[0] : 14 : output : 3.3-V LVTTL : : 1 : Y
pspdata[15] : 15 : output : 3.3-V LVTTL : : 1 : Y
pspdata[14] : 16 : output : 3.3-V LVTTL : : 1 : Y
GNDINT : 17 : gnd : : : :
clk : 18 : input : 3.3-V LVTTL : : 1 : Y
VCCINT : 19 : power : : 3.3V : :
pspdata[13] : 20 : output : 3.3-V LVTTL : : 1 : Y
pspdata[12] : 21 : output : 3.3-V LVTTL : : 1 : Y
pspdata[11] : 22 : output : 3.3-V LVTTL : : 1 : Y
pspdata[10] : 23 : output : 3.3-V LVTTL : : 1 : Y
pspdata[9] : 24 : output : 3.3-V LVTTL : : 1 : Y
VCCIO1 : 25 : power : : 3.3V : 1 :
GNDIO : 26 : gnd : : : :
pspdata[8] : 27 : output : 3.3-V LVTTL : : 1 : Y
pspdata[23] : 28 : output : 3.3-V LVTTL : : 1 : Y
pspdata[22] : 29 : output : 3.3-V LVTTL : : 1 : Y
pspdata[21] : 30 : output : 3.3-V LVTTL : : 1 : Y
pspdata[20] : 31 : output : 3.3-V LVTTL : : 1 : Y
pspdata[19] : 32 : output : 3.3-V LVTTL : : 1 : Y
TMS : 33 : input : : : 1 :
TDI : 34 : input : : : 1 :
TCK : 35 : input : : : 1 :
TDO : 36 : output : : : 1 :
pspdata[18] : 37 : output : 3.3-V LVTTL : : 1 : Y
pspdata[17] : 38 : output : 3.3-V LVTTL : : 1 : Y
pspdata[16] : 39 : output : 3.3-V LVTTL : : 1 : Y
wrdata[0] : 40 : input : 3.3-V LVTTL : : 1 : Y
wrdata[1] : 41 : input : 3.3-V LVTTL : : 1 : Y
wrdata[2] : 42 : input : 3.3-V LVTTL : : 1 : Y
wrdata[3] : 43 : input : 3.3-V LVTTL : : 1 : Y
wrdata[4] : 44 : input : 3.3-V LVTTL : : 1 : Y
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