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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.542 ns
From           : RamData[12]
To             : RamB0[12]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 20.637 ns
From           : LED~reg0
To             : LED
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.049 ns
From           : wrdata[15]
To             : WADDER[15]
From Clock     : --
To Clock       : WR
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : -4.219 ns
Required Time  : 54.00 MHz ( period = 18.518 ns )
Actual Time    : 37.10 MHz ( period = 26.956 ns )
From           : addstart
To             : RADDER[8]
From Clock     : clk
To Clock       : clk
Failed Paths   : 18

Type           : Clock Setup: 'WR'
Slack          : 4.426 ns
Required Time  : 54.00 MHz ( period = 18.518 ns )
Actual Time    : 70.96 MHz ( period = 14.092 ns )
From           : WADDER[5]
To             : wridata[9]
From Clock     : WR
To Clock       : WR
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : -2.556 ns
Required Time  : 54.00 MHz ( period = 18.518 ns )
Actual Time    : N/A
From           : RamB0[2]
To             : pspdata[18]~reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 84

Type           : Clock Hold: 'WR'
Slack          : 3.408 ns
Required Time  : 54.00 MHz ( period = 18.518 ns )
Actual Time    : N/A
From           : WADDER[17]
To             : WADDER[9]
From Clock     : WR
To Clock       : WR
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 102

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