?? mk60n512vmd100.h
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/*
** ###################################################################
** Processor: MK60N512VMD100
** Compilers: Freescale C/C++ for Embedded ARM
** IAR ANSI C/C++ Compiler for ARM
** Reference manual: K60P144M100SF2RM, Rev. 3, 4 Nov 2010
** Version: rev. 1.0, 2011-01-14
**
** Abstract:
** This header file implements peripheral memory map for MK60N512VMD100
** processor.
**
** Copyright: 1997 - 2011 Freescale Semiconductor, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 0.1 (2010-04-10)
** Initial version
** - rev. 0.2 (2010-08-31)
** TSI base address fixed
** - rev. 0.3 (2010-09-05)
** AXBS registers for unimplemented masters/slaves removed
** - rev. 0.4 (2010-09-06)
** Corrected operand type-cast in bit group REG_<regType>_<groupName>(x) macros according to MISRA rules.
** - rev. 0.5 (2010-09-24)
** Registers updated according to the new reference manual revision - Rev. 1, 10 Sept 2010
** CRC - 16-bit registers joined to 32-bit registers
** RTC - prefix of symbol for peripheral instance base addresses changed SRTC -> RTC
** LPTMR - change of register prefix - LPT0 -> LPTMR0
** SPI - HCR register removed
** TSI - STATUS register removed; THRESHLD0-15 registers removed; several bits of the SCANC register removed
** USB - change of register prefix USBOTG -> USB
** - rev. 0.6 (2010-10-01)
** CAN - Message buffers registers added (#MTWX43663)
** ENET - Statistic event counters registers added (#MTWX43372)
** TSI - THRESHLD0-15 registers reverted back
** - rev. 0.7 (2010-10-26)
** Added new #define symbols <periphInstance>_<regType>(index1,2,...) for macros accessing register arrays with fixed peripheral base address.
** - rev. 0.8 (2010-10-27)
** Registers updated according to the new reference manual revision - Rev. 2, 15 Oct 2010
** ADC - Peripheral register PGA bit definition has been fixed, bits PGALP, PGACHP removed.
** CAN - Peripheral register MCR bit definition has been fixed, bit WAKSRC removed.
** CRC - Peripheral register layout structure has been extended with 8/16-bit access to shadow registers.
** CMP - Peripheral base pointer macro renamed from HSCMPx_BASE_PTR to CMPx_BASE_PTR.
** DMA - Peripheral base pointer define macro name has been changed from eDMA_BASE_PTR to DMA_BASE_PTR.
** ENET - Statistic event counter register MASK and SHIFT macros removed (#MTWX43372).
** GPIO - Port Output Enable Register (POER) renamed to Port Data Direction Register (PDDR), all POER related macros fixed to PDDR.
** I2S - Prefix of register names changed from "I2S_" to "I2S0_".
** NV - Non-volatile Flash register FOPT bit definition redefined, FPROTx address and register names prefix fixed from "NV" to "F".
** PDB - Peripheral register layout structure has been extended for Channel n and DAC n register array access (#MTWX44115).
** PDB - Prefix of register accessor macro changed from "PDB_" to "PDB0_".
** RFSYS - System regfile registers have been added (#MTWX43999)
** RFVBAT - VBAT regfile registers have been added (#MTWX43999)
** RNG - Peripheral base pointer define macro name has been changed from RNGB_BASE_PTR to RNG_BASE_PTR.
** RTC - Peripheral register CR bit definition has been fixed, bit OTE removed.
** TSI - STATUS, SCANC register bit definition have been fixed, bit groups CAPTRM, DELVOL and AMCLKDIV added.
** TSI - Prefix of register names changed from "TSI_" to "TSI0_".
** USB - Peripheral base pointer define macro name has been changed USBOTG0_BASE_PTR to USB0_BASE_PTR.
** USB - Prefix of register names changed from "USBOTG0_" to "USB0_".
** VREF - Peripheral register TRM removed.
** - rev. 0.9 (2010-11-11)
** Registers updated according to the new reference manual revision - Rev. 3, 4 Nov 2010
** CAN - Support for INT_CANx_IMEU, INT_CANx_Lost_Rx interrupts has been removed.
** CAN - Individual Matching Element Update (IMEU) feature has been removed.
** CAN - Peripheral register layout structure has been fixed, registers IMEUR, LRFR have been removed.
** CAN - Peripheral register CTRL2 bit definition has been fixed, bits IMEUMASK, LOSTRMMSK, LOSTRLMSK, IMEUEN have been removed.
** CAN - Peripheral register ESR2 bit definition has been fixed, bits IMEUF, LOSTRMF, LOSTRLF have been removed.
** NV - Fixed offset address of BACKKEYx, FPROTx registers.
** TSI - Peripheral register layout structure has been fixed, register WUCNTR has been removed.
** - rev. 0.10 (2010-11-30)
** EWM - Peripheral base pointer EWM_BASE_PTR address has been fixed from 0x4005F000u to 0x40061000u (#MTWX44776).
** - rev. 0.11 (2010-12-17)
** AIPS0, AIPS1 - Fixed offset of PACRE-PACRP registers (#MTWX45259).
** CAU - Fixed register definition.
** - rev. 1.0 (2011-01-14)
** Added BITBAND_REG() macro to provide access to register bits using bit band region.
** Added checking of memory map version if two memory map files are included in a project (#MTWX45472).
**
** ###################################################################
*/
/*! \file MK60N512VMD100.h */
/*! \version 1.0 */
/*! \date 2011-01-14 */
/*! \brief Peripheral memory map for MK60N512VMD100 */
/*! \detailed This header file implements peripheral memory map for MK60N512VMD100
processor. */
/* ----------------------------------------------------------------------------
-- MCU activation
---------------------------------------------------------------------------- */
/* Prevention from multiple including the same memory map */
#if !defined(MCU_MK60N512VMD100) /* Check if memory map has not been already included */
#define MCU_MK60N512VMD100
/* Check if another memory map has not been also included */
#if (defined(MCU_ACTIVE))
#error MK60N512VMD100 memory map: There is already included another memory map. Only one memory map can be included.
#endif /* (defined(MCU_ACTIVE)) */
#define MCU_ACTIVE
#include <stdint.h>
/*! Memory map version 1.0 */
#define MCU_MEM_MAP_VERSION 0x0100u
/*!
* \def BITBAND_REG(reg,bit)
* \brief Macro to access a single bit of a peripheral register (bit band region 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
* \param Reg Register to access
* \param Bit Bit number to access
* \return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*! \addtogroup Interrupt_vector_numbers Interrupt vector numbers */
/*! \{ */
/*! Interrupt Number Definitions */
typedef enum {
INT_Initial_Stack_Pointer = 0, /*!< Initial stack pointer */
INT_Initial_Program_Counter = 1, /*!< Initial program counter */
INT_NMI = 2, /*!< Non-maskable interrupt */
INT_Hard_Fault = 3, /*!< Hard fault exception */
INT_Reserved4 = 4, /*!< Reserved interrupt 4 */
INT_Bus_Fault = 5, /*!< Bus fault exception */
INT_Usage_Fault = 6, /*!< Usage fault exception */
INT_Reserved7 = 7, /*!< Reserved interrupt 7 */
INT_Reserved8 = 8, /*!< Reserved interrupt 8 */
INT_Reserved9 = 9, /*!< Reserved interrupt 9 */
INT_Reserved10 = 10, /*!< Reserved interrupt 10 */
INT_SVCall = 11, /*!< A supervisor call exception */
INT_DebugMonitor = 12, /*!< Debug Monitor */
INT_Reserved13 = 13, /*!< Reserved interrupt 13 */
INT_PendableSrvReq = 14, /*!< PendSV exception - request for system level service */
INT_SysTick = 15, /*!< SysTick Interrupt */
INT_DMA0 = 16, /*!< DMA Channel 0 Transfer Complete */
INT_DMA1 = 17, /*!< DMA Channel 1 Transfer Complete */
INT_DMA2 = 18, /*!< DMA Channel 2 Transfer Complete */
INT_DMA3 = 19, /*!< DMA Channel 3 Transfer Complete */
INT_DMA4 = 20, /*!< DMA Channel 4 Transfer Complete */
INT_DMA5 = 21, /*!< DMA Channel 5 Transfer Complete */
INT_DMA6 = 22, /*!< DMA Channel 6 Transfer Complete */
INT_DMA7 = 23, /*!< DMA Channel 7 Transfer Complete */
INT_DMA8 = 24, /*!< DMA Channel 8 Transfer Complete */
INT_DMA9 = 25, /*!< DMA Channel 9 Transfer Complete */
INT_DMA10 = 26, /*!< DMA Channel 10 Transfer Complete */
INT_DMA11 = 27, /*!< DMA Channel 11 Transfer Complete */
INT_DMA12 = 28, /*!< DMA Channel 12 Transfer Complete */
INT_DMA13 = 29, /*!< DMA Channel 13 Transfer Complete */
INT_DMA14 = 30, /*!< DMA Channel 14 Transfer Complete */
INT_DMA15 = 31, /*!< DMA Channel 15 Transfer Complete */
INT_DMA_Error = 32, /*!< DMA Error Interrupt */
INT_MCM = 33, /*!< Normal Interrupt */
INT_FTFL = 34, /*!< FTFL Interrupt */
INT_Read_Collision = 35, /*!< Read Collision Interrupt */
INT_LVD_LVW = 36, /*!< Low Voltage Detect, Low Voltage Warning */
INT_LLW = 37, /*!< Low Leakage Wakeup */
INT_Watchdog = 38, /*!< WDOG Interrupt */
INT_RNG = 39, /*!< RNGB Interrupt */
INT_I2C0 = 40, /*!< I2C0 interrupt */
INT_I2C1 = 41, /*!< I2C1 interrupt */
INT_SPI0 = 42, /*!< SPI0 Interrupt */
INT_SPI1 = 43, /*!< SPI1 Interrupt */
INT_SPI2 = 44, /*!< SPI2 Interrupt */
INT_CAN0_ORed_Message_buffer = 45, /*!< CAN0 OR'd Message Buffers Interrupt */
INT_CAN0_Bus_Off = 46, /*!< CAN0 Bus Off Interrupt */
INT_CAN0_Error = 47, /*!< CAN0 Error Interrupt */
INT_CAN0_Tx_Warning = 48, /*!< CAN0 Tx Warning Interrupt */
INT_CAN0_Rx_Warning = 49, /*!< CAN0 Rx Warning Interrupt */
INT_CAN0_Wake_Up = 50, /*!< CAN0 Wake Up Interrupt */
INT_Reserved51 = 51, /*!< Reserved interrupt 51 */
INT_Reserved52 = 52, /*!< Reserved interrupt 52 */
INT_CAN1_ORed_Message_buffer = 53, /*!< CAN1 OR'd Message Buffers Interrupt */
INT_CAN1_Bus_Off = 54, /*!< CAN1 Bus Off Interrupt */
INT_CAN1_Error = 55, /*!< CAN1 Error Interrupt */
INT_CAN1_Tx_Warning = 56, /*!< CAN1 Tx Warning Interrupt */
INT_CAN1_Rx_Warning = 57, /*!< CAN1 Rx Warning Interrupt */
INT_CAN1_Wake_Up = 58, /*!< CAN1 Wake Up Interrupt */
INT_Reserved59 = 59, /*!< Reserved interrupt 59 */
INT_Reserved60 = 60, /*!< Reserved interrupt 60 */
INT_UART0_RX_TX = 61, /*!< UART0 Receive/Transmit interrupt */
INT_UART0_ERR = 62, /*!< UART0 Error interrupt */
INT_UART1_RX_TX = 63, /*!< UART1 Receive/Transmit interrupt */
INT_UART1_ERR = 64, /*!< UART1 Error interrupt */
INT_UART2_RX_TX = 65, /*!< UART2 Receive/Transmit interrupt */
INT_UART2_ERR = 66, /*!< UART2 Error interrupt */
INT_UART3_RX_TX = 67, /*!< UART3 Receive/Transmit interrupt */
INT_UART3_ERR = 68, /*!< UART3 Error interrupt */
INT_UART4_RX_TX = 69, /*!< UART4 Receive/Transmit interrupt */
INT_UART4_ERR = 70, /*!< UART4 Error interrupt */
INT_UART5_RX_TX = 71, /*!< UART5 Receive/Transmit interrupt */
INT_UART5_ERR = 72, /*!< UART5 Error interrupt */
INT_ADC0 = 73, /*!< ADC0 interrupt */
INT_ADC1 = 74, /*!< ADC1 interrupt */
INT_CMP0 = 75, /*!< CMP0 interrupt */
INT_CMP1 = 76, /*!< CMP1 interrupt */
INT_CMP2 = 77, /*!< CMP2 interrupt */
INT_FTM0 = 78, /*!< FTM0 fault, overflow and channels interrupt */
INT_FTM1 = 79, /*!< FTM1 fault, overflow and channels interrupt */
INT_FTM2 = 80, /*!< FTM2 fault, overflow and channels interrupt */
INT_CMT = 81, /*!< CMT interrupt */
INT_RTC = 82, /*!< RTC interrupt */
INT_Reserved83 = 83, /*!< Reserved interrupt 83 */
INT_PIT0 = 84, /*!< PIT timer channel 0 interrupt */
INT_PIT1 = 85, /*!< PIT timer channel 1 interrupt */
INT_PIT2 = 86, /*!< PIT timer channel 2 interrupt */
INT_PIT3 = 87, /*!< PIT timer channel 3 interrupt */
INT_PDB0 = 88, /*!< PDB0 Interrupt */
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