?? mk60n512vmd100.h
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INT_USB0 = 89, /*!< USB0 interrupt */
INT_USBDCD = 90, /*!< USBDCD Interrupt */
INT_ENET_1588_Timer = 91, /*!< Ethernet MAC IEEE 1588 Timer Interrupt */
INT_ENET_Transmit = 92, /*!< Ethernet MAC Transmit Interrupt */
INT_ENET_Receive = 93, /*!< Ethernet MAC Receive Interrupt */
INT_ENET_Error = 94, /*!< Ethernet MAC Error and miscelaneous Interrupt */
INT_I2S0 = 95, /*!< I2S0 Interrupt */
INT_SDHC = 96, /*!< SDHC Interrupt */
INT_DAC0 = 97, /*!< DAC0 interrupt */
INT_DAC1 = 98, /*!< DAC1 interrupt */
INT_TSI0 = 99, /*!< TSI0 Interrupt */
INT_MCG = 100, /*!< MCG Interrupt */
INT_LPTimer = 101, /*!< LPTimer interrupt */
INT_Reserved102 = 102, /*!< Reserved interrupt 102 */
INT_PORTA = 103, /*!< Port A interrupt */
INT_PORTB = 104, /*!< Port B interrupt */
INT_PORTC = 105, /*!< Port C interrupt */
INT_PORTD = 106, /*!< Port D interrupt */
INT_PORTE = 107, /*!< Port E interrupt */
INT_Reserved108 = 108, /*!< Reserved interrupt 108 */
INT_Reserved109 = 109, /*!< Reserved interrupt 109 */
INT_Reserved110 = 110, /*!< Reserved interrupt 110 */
INT_Reserved111 = 111, /*!< Reserved interrupt 111 */
INT_Reserved112 = 112, /*!< Reserved interrupt 112 */
INT_Reserved113 = 113, /*!< Reserved interrupt 113 */
INT_Reserved114 = 114, /*!< Reserved interrupt 114 */
INT_Reserved115 = 115, /*!< Reserved interrupt 115 */
INT_Reserved116 = 116, /*!< Reserved interrupt 116 */
INT_Reserved117 = 117, /*!< Reserved interrupt 117 */
INT_Reserved118 = 118, /*!< Reserved interrupt 118 */
INT_Reserved119 = 119 /*!< Reserved interrupt 119 */
} IRQInterruptIndex;
/*! \} */ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Peripheral type defines
---------------------------------------------------------------------------- */
/*! \addtogroup Peripheral_defines Peripheral type defines */
/*! \{ */
/*
** Start of section using anonymous unions
*/
#if defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC
---------------------------------------------------------------------------- */
/*! \addtogroup ADC_Peripheral ADC */
/*! \{ */
/*! ADC - Peripheral register structure */
typedef struct ADC_MemMap {
uint32_t SC1[2]; /*!< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
uint32_t CFG1; /*!< ADC configuration register 1, offset: 0x8 */
uint32_t CFG2; /*!< Configuration register 2, offset: 0xC */
uint32_t R[2]; /*!< ADC data result register, array offset: 0x10, array step: 0x4 */
uint32_t CV1; /*!< Compare value registers, offset: 0x18 */
uint32_t CV2; /*!< Compare value registers, offset: 0x1C */
uint32_t SC2; /*!< Status and control register 2, offset: 0x20 */
uint32_t SC3; /*!< Status and control register 3, offset: 0x24 */
uint32_t OFS; /*!< ADC offset correction register, offset: 0x28 */
uint32_t PG; /*!< ADC plus-side gain register, offset: 0x2C */
uint32_t MG; /*!< ADC minus-side gain register, offset: 0x30 */
uint32_t CLPD; /*!< ADC plus-side general calibration value register, offset: 0x34 */
uint32_t CLPS; /*!< ADC plus-side general calibration value register, offset: 0x38 */
uint32_t CLP4; /*!< ADC plus-side general calibration value register, offset: 0x3C */
uint32_t CLP3; /*!< ADC plus-side general calibration value register, offset: 0x40 */
uint32_t CLP2; /*!< ADC plus-side general calibration value register, offset: 0x44 */
uint32_t CLP1; /*!< ADC plus-side general calibration value register, offset: 0x48 */
uint32_t CLP0; /*!< ADC plus-side general calibration value register, offset: 0x4C */
uint32_t PGA; /*!< ADC PGA register, offset: 0x50 */
uint32_t CLMD; /*!< ADC minus-side general calibration value register, offset: 0x54 */
uint32_t CLMS; /*!< ADC minus-side general calibration value register, offset: 0x58 */
uint32_t CLM4; /*!< ADC minus-side general calibration value register, offset: 0x5C */
uint32_t CLM3; /*!< ADC minus-side general calibration value register, offset: 0x60 */
uint32_t CLM2; /*!< ADC minus-side general calibration value register, offset: 0x64 */
uint32_t CLM1; /*!< ADC minus-side general calibration value register, offset: 0x68 */
uint32_t CLM0; /*!< ADC minus-side general calibration value register, offset: 0x6C */
} volatile *ADC_MemMapPtr;
/* ----------------------------------------------------------------------------
-- ADC - Register accessor macros
---------------------------------------------------------------------------- */
/*! \addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros */
/*! \{ */
/* ADC - Register accessors */
#define ADC_SC1_REG(base,index) ((base)->SC1[index])
#define ADC_CFG1_REG(base) ((base)->CFG1)
#define ADC_CFG2_REG(base) ((base)->CFG2)
#define ADC_R_REG(base,index) ((base)->R[index])
#define ADC_CV1_REG(base) ((base)->CV1)
#define ADC_CV2_REG(base) ((base)->CV2)
#define ADC_SC2_REG(base) ((base)->SC2)
#define ADC_SC3_REG(base) ((base)->SC3)
#define ADC_OFS_REG(base) ((base)->OFS)
#define ADC_PG_REG(base) ((base)->PG)
#define ADC_MG_REG(base) ((base)->MG)
#define ADC_CLPD_REG(base) ((base)->CLPD)
#define ADC_CLPS_REG(base) ((base)->CLPS)
#define ADC_CLP4_REG(base) ((base)->CLP4)
#define ADC_CLP3_REG(base) ((base)->CLP3)
#define ADC_CLP2_REG(base) ((base)->CLP2)
#define ADC_CLP1_REG(base) ((base)->CLP1)
#define ADC_CLP0_REG(base) ((base)->CLP0)
#define ADC_PGA_REG(base) ((base)->PGA)
#define ADC_CLMD_REG(base) ((base)->CLMD)
#define ADC_CLMS_REG(base) ((base)->CLMS)
#define ADC_CLM4_REG(base) ((base)->CLM4)
#define ADC_CLM3_REG(base) ((base)->CLM3)
#define ADC_CLM2_REG(base) ((base)->CLM2)
#define ADC_CLM1_REG(base) ((base)->CLM1)
#define ADC_CLM0_REG(base) ((base)->CLM0)
/*! \} */ /* end of group ADC_Register_Accessor_Macros */
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/*! \addtogroup ADC_Register_Masks ADC Register Masks */
/*! \{ */
/* SC1 Bit Fields */
#define ADC_SC1_ADCH_MASK 0x1Fu
#define ADC_SC1_ADCH_SHIFT 0
#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
#define ADC_SC1_DIFF_MASK 0x20u
#define ADC_SC1_DIFF_SHIFT 5
#define ADC_SC1_AIEN_MASK 0x40u
#define ADC_SC1_AIEN_SHIFT 6
#define ADC_SC1_COCO_MASK 0x80u
#define ADC_SC1_COCO_SHIFT 7
/* CFG1 Bit Fields */
#define ADC_CFG1_ADICLK_MASK 0x3u
#define ADC_CFG1_ADICLK_SHIFT 0
#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
#define ADC_CFG1_MODE_MASK 0xCu
#define ADC_CFG1_MODE_SHIFT 2
#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
#define ADC_CFG1_ADLSMP_MASK 0x10u
#define ADC_CFG1_ADLSMP_SHIFT 4
#define ADC_CFG1_ADIV_MASK 0x60u
#define ADC_CFG1_ADIV_SHIFT 5
#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
#define ADC_CFG1_ADLPC_MASK 0x80u
#define ADC_CFG1_ADLPC_SHIFT 7
/* CFG2 Bit Fields */
#define ADC_CFG2_ADLSTS_MASK 0x3u
#define ADC_CFG2_ADLSTS_SHIFT 0
#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
#define ADC_CFG2_ADHSC_MASK 0x4u
#define ADC_CFG2_ADHSC_SHIFT 2
#define ADC_CFG2_ADACKEN_MASK 0x8u
#define ADC_CFG2_ADACKEN_SHIFT 3
#define ADC_CFG2_MUXSEL_MASK 0x10u
#define ADC_CFG2_MUXSEL_SHIFT 4
/* R Bit Fields */
#define ADC_R_D_MASK 0xFFFFu
#define ADC_R_D_SHIFT 0
#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
/* CV1 Bit Fields */
#define ADC_CV1_CV_MASK 0xFFFFu
#define ADC_CV1_CV_SHIFT 0
#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
/* CV2 Bit Fields */
#define ADC_CV2_CV_MASK 0xFFFFu
#define ADC_CV2_CV_SHIFT 0
#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
/* SC2 Bit Fields */
#define ADC_SC2_REFSEL_MASK 0x3u
#define ADC_SC2_REFSEL_SHIFT 0
#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
#define ADC_SC2_DMAEN_MASK 0x4u
#define ADC_SC2_DMAEN_SHIFT 2
#define ADC_SC2_ACREN_MASK 0x8u
#define ADC_SC2_ACREN_SHIFT 3
#define ADC_SC2_ACFGT_MASK 0x10u
#define ADC_SC2_ACFGT_SHIFT 4
#define ADC_SC2_ACFE_MASK 0x20u
#define ADC_SC2_ACFE_SHIFT 5
#define ADC_SC2_ADTRG_MASK 0x40u
#define ADC_SC2_ADTRG_SHIFT 6
#define ADC_SC2_ADACT_MASK 0x80u
#define ADC_SC2_ADACT_SHIFT 7
/* SC3 Bit Fields */
#define ADC_SC3_AVGS_MASK 0x3u
#define ADC_SC3_AVGS_SHIFT 0
#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
#define ADC_SC3_AVGE_MASK 0x4u
#define ADC_SC3_AVGE_SHIFT 2
#define ADC_SC3_ADCO_MASK 0x8u
#define ADC_SC3_ADCO_SHIFT 3
#define ADC_SC3_CALF_MASK 0x40u
#define ADC_SC3_CALF_SHIFT 6
#define ADC_SC3_CAL_MASK 0x80u
#define ADC_SC3_CAL_SHIFT 7
/* OFS Bit Fields */
#define ADC_OFS_OFS_MASK 0xFFFFu
#define ADC_OFS_OFS_SHIFT 0
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