Release 7.1i - xst H.38Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.42 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.42 s | Elapsed : 0.00 / 0.00 s --> Reading design: syv.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "syv.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "syv"Output Format                      : NGCTarget Device                      : xc2s50-6-tq144---- Source OptionsTop Module Name                    : syvAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : lutAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 100Add Generic Clock Buffer(BUFG)     : 4Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : syv.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOtristate2logic                     : Yesuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yesenable_auto_floorplanning          : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "syv.v"Module <syv> compiledNo errors in compilationAnalysis of file <"syv.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <syv>.Module <syv> is correct for synthesis.     Set property "resynthesize = true" for unit <syv>.=========================================================================*                           HDL Synthesis                               *=========================================================================INFO:Xst:1304 - Contents of register <w_addr24> in unit <syv> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <ce> in unit <syv> never changes during circuit operation. The register is replaced by logic.Synthesizing Unit <syv>.    Related source file is "syv.v".WARNING:Xst:1306 - Output <led2> is never assigned.WARNING:Xst:1305 - Output <usbtxe> is never assigned. Tied to value 0.WARNING:Xst:1780 - Signal <led2_3> is never used or assigned.WARNING:Xst:1780 - Signal <da_tp2> is never used or assigned.WARNING:Xst:646 - Signal <usbtxein> is assigned but never used.    Found finite state machine <FSM_0> for signal <st_wr>.    -----------------------------------------------------------------------    | States             | 64                                             |    | Transitions        | 71                                             |    | Inputs             | 6                                              |    | Outputs            | 64                                             |    | Clock              | div_clock_t (rising_edge)                      |    | Reset              | sys_reset (positive)                           |    | Reset type         | synchronous                                    |    | Reset State        | 000000                                         |    | Power Up State     | 000000                                         |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found 1-bit register for signal <led_rd4>.    Found 19-bit register for signal <memaddr>.    Found 1-bit register for signal <div_clock>.    Found 1-bit register for signal <led_chip1>.    Found 1-bit register for signal <datam25_in>.    Found 1-bit register for signal <s_m25>.    Found 1-bit register for signal <wr_mem>.    Found 1-bit 8-to-1 multiplexer for signal <$COND_1>.    Found 15-bit comparator less for signal <$n0001> created at line 354.    Found 5-bit comparator less for signal <$n0002> created at line 443.    Found 5-bit comparator less for signal <$n0003> created at line 454.    Found 9-bit comparator less for signal <$n0004> created at line 464.    Found 6-bit comparator less for signal <$n0005> created at line 479.    Found 5-bit comparator less for signal <$n0006> created at line 557.    Found 24-bit comparator lessequal for signal <$n0071> created at line 114.    Found 1-bit 4-to-1 multiplexer for signal <$n0080>.    Found 5-bit adder for signal <$n0103> created at line 457.    Found 5-bit adder for signal <$n0104>.    Found 9-bit adder for signal <$n0105> created at line 467.    Found 6-bit adder for signal <$n0106> created at line 481.    Found 5-bit adder for signal <$n0107> created at line 560.    Found 19-bit adder for signal <$n0108> created at line 567.    Found 2-bit up counter for signal <count>.    Found 15-bit up counter for signal <count_era>.    Found 6-bit register for signal <count_pp>.    Found 10-bit up counter for signal <counter_6M>.    Found 8-bit register for signal <da_tp1>.    Found 8-bit register for signal <da_tp3>.    Found 1-bit register for signal <div_clock_t>.    Found 5-bit register for signal <f>.    Found 5-bit register for signal <i>.    Found 5-bit register for signal <j>.    Found 9-bit register for signal <k>.    Found 24-bit up counter for signal <resetcount>.    Found 1-bit register for signal <sys_reset>.    Found 1-bit register for signal <txeflag>.    Summary:	inferred   1 Finite State Machine(s).	inferred   4 Counter(s).	inferred  74 D-type flip-flop(s).	inferred   6 Adder/Subtractor(s).	inferred   7 Comparator(s).	inferred   2 Multiplexer(s).Unit <syv> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <FSM_0> on signal <st_wr[1:64]> with speed1 encoding.---------------------------------------------------------------------------- State  | Encoding---------------------------------------------------------------------------- 000000 | 1000000000000000000000000000000000000000000000000000000000000000 000001 | 0100000000000000000000000000000000000000000000000000000000000000 000010 | 0010000000000000000000000000000000000000000000000000000000000000 000011 | 0001000000000000000000000000000000000000000000000000000000000000 000100 | 0000100000000000000000000000000000000000000000000000000000000000 000101 | 0000010000000000000000000000000000000000000000000000000000000000 000110 | 0000001000000000000000000000000000000000000000000000000000000000 000111 | 0000000100000000000000000000000000000000000000000000000000000000 001000 | 0000000010000000000000000000000000000000000000000000000000000000 001001 | 0000000001000000000000000000000000000000000000000000000000000000 001010 | 0000000000100000000000000000000000000000000000000000000000000000 001011 | 0000000000010000000000000000000000000000000000000000000000000000 001100 | 0000000000001000000000000000000000000000000000000000000000000000 001101 | 0000000000000100000000000000000000000000000000000000000000000000 001110 | 0000000000000010000000000000000000000000000000000000000000000000 001111 | 0000000000000000100000000000000000000000000000000000000000000000 010000 | 0000000000000000001000000000000000000000000000000000000000000000 010001 | 0000000000000000000010000000000000000000000000000000000000000000 010010 | 0000000000000000000000100000000000000000000000000000000000000000 010011 | 0000000000000000000000001000000000000000000000000000000000000000 010100 | 0000000000000001000000000000000000000000000000000000000000000000 010101 | 0000000000000000010000000000000000000000000000000000000000000000 010110 | 0000000000000000000100000000000000000000000000000000000000000000 010111 | 0000000000000000000001000000000000000000000000000000000000000000 011000 | 0000000000000000000000010000000000000000000000000000000000000000 011001 | 0000000000000000000000000100000000000000000000000000000000000000 011010 | 0000000000000000000000000000100000000000000000000000000000000000 011011 | 0000000000000000000000000000001000000000000000000000000000000000 011100 | 0000000000000000000000000000000010000000000000000000000000000000 011101 | 0000000000000000000000000000000000100000000000000000000000000000 011110 | 0000000000000000000000000010000000000000000000000000000000000000 011111 | 0000000000000000000000000001000000000000000000000000000000000000 100000 | 0000000000000000000000000000010000000000000000000000000000000000 100001 | 0000000000000000000000000000000100000000000000000000000000000000 100010 | 0000000000000000000000000000000001000000000000000000000000000000 100011 | 0000000000000000000000000000000000001000000000000000000000000000 100100 | 0000000000000000000000000000000000000010000000000000000000000000 100101 | 0000000000000000000000000000000000000000100000000000000000000000 100110 | 0000000000000000000000000000000000000000001000000000000000000000 100111 | 0000000000000000000000000000000000000000000010000000000000000000 101000 | 0000000000000000000000000000000000010000000000000000000000000000 101001 | 0000000000000000000000000000000000000100000000000000000000000000 101010 | 0000000000000000000000000000000000000001000000000000000000000000 101011 | 0000000000000000000000000000000000000000010000000000000000000000 101100 | 0000000000000000000000000000000000000000000100000000000000000000 101101 | 0000000000000000000000000000000000000000000000100000000000000000 101110 | 0000000000000000000000000000000000000000000000001000000000000000 101111 | 0000000000000000000000000000000000000000000000000010000000000000 110000 | 0000000000000000000000000000000000000000000000000000100000000000 110001 | 0000000000000000000000000000000000000000000000000000001000000000 110010 | 0000000000000000000000000000000000000000000001000000000000000000 110011 | 0000000000000000000000000000000000000000000000010000000000000000 110100 | 0000000000000000000000000000000000000000000000000100000000000000 110101 | 0000000000000000000000000000000000000000000000000001000000000000 110110 | 0000000000000000000000000000000000000000000000000000010000000000 110111 | 0000000000000000000000000000000000000000000000000000000010000000 111000 | 0000000000000000000000000000000000000000000000000000000000100000 111001 | 0000000000000000000000000000000000000000000000000000000000001000 111010 | 0000000000000000000000000000000000000000000000000000000000000100 111011 | 0000000000000000000000000000000000000000000000000000000000000001 111100 | 0000000000000000000000000000000000000000000000000000000100000000 111101 | 0000000000000000000000000000000000000000000000000000000001000000 111110 | 0000000000000000000000000000000000000000000000000000000000010000 111111 | 0000000000000000000000000000000000000000000000000000000000000010----------------------------------------------------------------------------Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs                             : 1# Adders/Subtractors               : 6 19-bit adder                      : 1