Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 25 unexpected token: ';'ERROR:HDLCompilers:207 - "syv.v" line 39 Signal 'global_clock' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 41 Signal 'ads781_sh' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 43 Signal 'ads8401_cs' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 44 Signal 'ads8401_rd' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 45 Signal 'ads8401_convst' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 46 Signal 'ads8401_byte' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 47 Signal 'ads8401_reset' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 48 Signal 'ads8401_data' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 50 Signal 'adg706_addr' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 51 Signal 'fifo1_wen' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 52 Signal 'fifo1_wclk' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 53 Signal 'fifo1_prs' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 54 Signal 'fifo1_mrs' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 55 Signal 'fifo1_ld' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 56 Signal 'fifo1_fsel0' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 57 Signal 'fifo1_fsel1' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 58 Signal 'fifo1_pfm' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 59 Signal 'fifo1_ren' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 60 Signal 'fifo1_rclk' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 61 Signal 'fifo1_oe' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 62 Signal 'fifo1_hf' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 63 Signal 'fifo1_data' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 65 Signal 'fifo2_wr' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 67 Signal 'dsp_reset' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 68 Signal 'dsp_extint5' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 69 Signal 'dsp_aoe' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 70 Signal 'dsp_awe' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 71 Signal 'dsp_are' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 72 Signal 'dsp_tce2' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 73 Signal 'dsp_tce3' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 74 Signal 'dsp_watchdog' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 75 Signal 'dsp_gp10' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 77 Signal 'flash_oe' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 78 Signal 'flash_we' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 79 Signal 'flash_reset' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 81 Signal 'led1' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 82 Signal 'resetsend' is not referenced in the module port listERROR:HDLCompilers:28 - "syv.v" line 102 'dsp_tce2' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 102 'dsp_aoe' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 103 'dsp_are' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 103 'dsp_tce2' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 104 'dsp_tce2' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 104 'dsp_aoe' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 107 'dsp_awe' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 107 'dsp_tce3' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 112 'resetsend' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 114 'dsp_aoe' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 115 'dsp_awe' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 135 'global_clock' has not been declaredERROR:HDLCompilers:26 - "syv.v" line 152 expecting 'end', found 'endmodule'ERROR:HDLCompilers:26 - "syv.v" line 153 unexpected token: 'EOF'ERROR:HDLCompilers:26 - "syv.v" line 153 expecting 'end', found 'EOF'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 153 expecting 'endmodule', found 'EOF'Analysis of file <"syv.prj"> failed.--> Total memory usage is 77056 kilobytesNumber of errors   :   54 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 24 unexpected token: ';'ERROR:HDLCompilers:207 - "syv.v" line 36 Signal 'global_clock' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 38 Signal 'clk_m25' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 40 Signal 'data_in' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 41 Signal 'datam25_out' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 42 Signal 'datam25_in' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 44 Signal 's_m25' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 45 Signal 'wr' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 46 Signal 'hold_m25' is not referenced in the module port listERROR:HDLCompilers:28 - "syv.v" line 68 'global_clock' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 70 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 72 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 72 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 74 'sys_reset' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 76 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 78 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 78 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 80 'sys_reset' has not been declaredERROR:HDLCompilers:26 - "syv.v" line 84 expecting 'end', found 'always'ERROR:HDLCompilers:28 - "syv.v" line 84 'global_clock' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 85 'sys_reset' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 87 'counter_6M' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 88 'div_clock' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 92 'counter_6M' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 94 'counter_6M' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 95 'div_clock' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 95 'div_clock' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 100 'counter_50M' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 100 'counter_50M' has not been declaredERROR:HDLCompilers:26 - "syv.v" line 103 expecting 'end', found 'always'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 103 expecting 'endmodule', found '@'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76992 kilobytesNumber of errors   :   31 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------

Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 24 unexpected token: ';'ERROR:HDLCompilers:207 - "syv.v" line 36 Signal 'global_clock' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 38 Signal 'clk_m25' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 40 Signal 'data_in' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 41 Signal 'datam25_out' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 42 Signal 'datam25_in' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 44 Signal 's_m25' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 45 Signal 'wr' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 46 Signal 'hold_m25' is not referenced in the module port listERROR:HDLCompilers:28 - "syv.v" line 68 'global_clock' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 70 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 72 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 72 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 74 'sys_reset' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 76 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 78 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 78 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 80 'sys_reset' has not been declaredERROR:HDLCompilers:26 - "syv.v" line 84 expecting 'end', found 'always'ERROR:HDLCompilers:28 - "syv.v" line 84 'global_clock' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 85 'sys_reset' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 87 'counter_6M' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 88 'div_clock' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 92 'counter_6M' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 94 'counter_6M' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 95 'div_clock' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 95 'div_clock' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 100 'counter_50M' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 100 'counter_50M' has not been declaredERROR:HDLCompilers:26 - "syv.v" line 103 expecting 'end', found 'always'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 103 expecting 'endmodule', found '@'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors   :   31 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 24 unexpected token: ';'ERROR:HDLCompilers:207 - "syv.v" line 35 Signal 'global_clock' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 37 Signal 'clk_m25' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 39 Signal 'data_in' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 40 Signal 'datam25_out' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 41 Signal 'datam25_in' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 43 Signal 's_m25' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 44 Signal 'wr' is not referenced in the module port listERROR:HDLCompilers:207 - "syv.v" line 45 Signal 'hold_m25' is not referenced in the module port listERROR:HDLCompilers:28 - "syv.v" line 67 'global_clock' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 69 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 71 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 71 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 73 'sys_reset' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 77 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 77 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 79 'sys_reset' has not been declaredERROR:HDLCompilers:26 - "syv.v" line 83 expecting 'end', found 'always'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 83 expecting 'endmodule', found '@'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors   :   19 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:207 - "syv.v" line 44 Signal 'wr' is not referenced in the module port listERROR:HDLCompilers:28 - "syv.v" line 69 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 71 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 71 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 73 'sys_reset' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 77 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 77 'resetcount' has not been declaredERROR:HDLCompilers:28 - "syv.v" line 79 'sys_reset' has not been declaredERROR:HDLCompilers:26 - "syv.v" line 83 expecting 'end', found 'always'ERROR:HDLCompilers:208 - "syv.v" line 26 Port reference 'w_m25' was not declared as input, inout or outputERROR:HDLCompilers:208 - "syv.v" line 29 Port reference 'led1' was not declared as input, inout or outputERROR:HDLCompilers:208 - "syv.v" line 24 Port reference 'div_clock' was not declared as input, inout or output