Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 257 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 257 expecting '=', found '+'ERROR:HDLCompilers:26 - "syv.v" line 266 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 266 expecting '=', found '+'ERROR:HDLCompilers:26 - "syv.v" line 268 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 268 expecting '=', found '+'ERROR:HDLCompilers:26 - "syv.v" line 316 expecting 'end', found 'endmodule'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 317 expecting 'endmodule', found 'EOF'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors   :    8 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 257 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 257 expecting '=', found '+'ERROR:HDLCompilers:26 - "syv.v" line 266 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 266 expecting '=', found '+'ERROR:HDLCompilers:26 - "syv.v" line 268 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 268 expecting '=', found '+'ERROR:HDLCompilers:26 - "syv.v" line 316 expecting 'end', found 'endmodule'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 317 expecting 'endmodule', found 'EOF'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors   :    8 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 257 expecting '=', found '+'ERROR:HDLCompilers:26 - "syv.v" line 266 expecting '=', found '+'ERROR:HDLCompilers:26 - "syv.v" line 268 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 268 expecting '=', found '+'ERROR:HDLCompilers:26 - "syv.v" line 316 expecting 'end', found 'endmodule'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 317 expecting 'endmodule', found 'EOF'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors   :    6 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 268 expecting '=', found '=='ERROR:HDLCompilers:26 - "syv.v" line 316 expecting 'end', found 'endmodule'Module <syv> compiledERROR:HDLCompilers:26 - "syv.v" line 317 expecting 'endmodule', found 'EOF'Analysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors   :    3 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "syv.v"Module <syv> compiledERROR:HDLCompilers:247 - "syv.v" line 91 Reference to scalar wire 'div_clock' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 91 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 98 Reference to scalar wire 'div_clock' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 98 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 112 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 112 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 115 Reference to scalar wire 'led1' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 115 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 122 Reference to scalar wire 'led1' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 122 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 127 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 127 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 133 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 133 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 138 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 138 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 143 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 143 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 148 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 148 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 153 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 153 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 158 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 158 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 163 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 163 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 169 Reference to scalar wire 'led1' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 169 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 184 Reference to scalar wire 'led1' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 184 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 189 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 189 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 196 Reference to scalar wire 'led1' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 196 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 212 Reference to scalar wire 'led1' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 212 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 217 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 217 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 222 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 222 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 227 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 227 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 232 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 232 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 237 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 237 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 242 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 242 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 247 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 247 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 252 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 252 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 259 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 259 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 269 Reference to scalar wire 'datam25_in' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 269 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "syv.v" line 276 Reference to scalar wire 'led1' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "syv.v" line 276 Illegal left hand side of nonblocking assignmentAnalysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors   :   58 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "syv.v"ERROR:HDLCompilers:26 - "syv.v" line 53 unexpected token: 'div_clock'ERROR:HDLCompilers:26 - "syv.v" line 53 expecting '=', found ';'ERROR:HDLCompilers:27 - "syv.v" line 69 Illegal redeclaration of 'div_clock_t'Module <syv> compiledAnalysis of file <"syv.prj"> failed.--> Total memory usage is 76764 kilobytesNumber of errors   :    3 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------