Release 7.1i Map H.38Xilinx Mapping Report File for Design 'syv'Design Information------------------Command Line   : C:/Xilinx/bin/nt/map.exe -ise e:\whao_dyz_cpld\syv\syv.ise
-intstyle ise -p xc2s50-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o
syv_map.ncd syv.ngd syv.pcf Target Device  : xc2s50Target Package : tq144Target Speed   : -6Mapper Version : spartan2 -- $Revision: 1.26.6.3 $Mapped Date    : Sun May 25 12:39:20 2008Design Summary--------------Number of errors:      0Number of warnings:    2Logic Utilization:  Number of Slice Flip Flops:       145 out of  1,536    9%  Number of 4 input LUTs:            86 out of  1,536    5%Logic Distribution:    Number of occupied Slices:                         122 out of    768   15%    Number of Slices containing only related logic:    122 out of    122  100%    Number of Slices containing unrelated logic:         0 out of    122    0%        *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:          158 out of  1,536   10%      Number used as logic:                        86      Number used as a route-thru:                 72   Number of bonded IOBs:            16 out of     92   17%   Number of GCLKs:                   2 out of      4   50%   Number of GCLKIOBs:                1 out of      4   25%Total equivalent gate count for design:  2,126Additional JTAG gate count for IOBs:  816Peak Memory Usage:  95 MBNOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin packing   unrelated logic into a slice once 99% of the slices are occupied through   related logic packing.   Note that once logic distribution reaches the 99% level through related   logic packing, this does not mean the device is completely utilized.   Unrelated logic packing will then begin, continuing until all usable LUTs   and FFs are occupied.  Depending on your timing budget, increased levels of   unrelated logic packing may adversely affect the overall timing performance   of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:LIT:243 - Logical network datam25_out_IBUF has no load.WARNING:PhysDesignRules:367 - The signal <datam25_out_IBUF> is incomplete. The
   signal does not drive any load pins in the design.Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.Section 4 - Removed Logic Summary---------------------------------   2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE 		BLOCKGND 		XST_GNDVCC 		XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| global_clk                         | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       || data_in<0>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       || data_in<1>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       || data_in<2>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       || data_in<3>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       || data_in<4>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       || data_in<5>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       || data_in<6>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       || data_in<7>                         | IOB     | INPUT     | LVTTL       |          |      |          |          |       || datam25_in                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || datam25_out                        | IOB     | INPUT     | LVTTL       |          |      |          |          |       || div_clock                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || hold_m25                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || led1                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || led2                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || s_m25                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || w_m25                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 17Number of Equivalent Gates for Design = 2,126Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 2Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 118IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 0Unbonded IOBs = 0Bonded IOBs = 16XORs = 70CARRY_INITs = 44CARRY_SKIPs = 0CARRY_MUXes = 77Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULT_ANDs = 0MUXF5s + MUXF6s = 34 input LUTs used as Route-Thrus = 724 input LUTs = 86Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 118Slice Flip Flops = 145Slices = 122F6 Muxes = 1F5 Muxes = 2Number of LUT signals with 4 loads = 1Number of LUT signals with 3 loads = 5Number of LUT signals with 2 loads = 10Number of LUT signals with 1 load = 62NGM Average fanout of LUT = 1.98NGM Maximum fanout of LUT = 15NGM Average fanin for LUT = 2.9535Number of LUT symbols = 86