#define MCBSP_MK_SPCR(rrst,rintm,dxena,clkstp,rjust,dlb,xrst,xintm,grst,\    frst) ((Uint32)( \      HFIELD_SHIFT(HMCBSP_SPCR_RRST,rrst)| \      HFIELD_SHIFT(HMCBSP_SPCR_RINTM,rintm)| \      HFIELD_SHIFT(HMCBSP_SPCR_DXENA,dxena)| \      HFIELD_SHIFT(HMCBSP_SPCR_CLKSTP,clkstp)| \      HFIELD_SHIFT(HMCBSP_SPCR_RJUST,rjust)| \      HFIELD_SHIFT(HMCBSP_SPCR_DLB,dlb)| \      HFIELD_SHIFT(HMCBSP_SPCR_XRST,xrst)| \      HFIELD_SHIFT(HMCBSP_SPCR_XINTM,xintm)| \      HFIELD_SHIFT(HMCBSP_SPCR_GRST,grst)| \      HFIELD_SHIFT(HMCBSP_SPCR_FRST,frst) \    ) \  )/******** redefined for CSL 1.2 / 1.23 ************/  #define _MCBSP_RCR_RPHASE2_MASK      0x00008000u  #define _MCBSP_RCR_RPHASE2_SHIFT     0x0000000Fu  #define  MCBSP_RCR_RPHASE2_DEFAULT   0x00000000u  #define  MCBSP_RCR_RPHASE2_OF(x)     _VALUEOF(x)    #define _MCBSP_XCR_XPHASE2_MASK      0x00008000u  #define _MCBSP_XCR_XPHASE2_SHIFT     0x0000000Fu  #define  MCBSP_XCR_XPHASE2_DEFAULT   0x00000000u  #define  MCBSP_XCR_XPHASE2_OF(x)     _VALUEOF(x)  #define MCBSP_MK_RCR(rwdrevrs,rwdlen1,rfrlen1,rphase2,rdatdly,rfig,\    rcompand,rwdlen2,rfrlen2,rphase) ((Uint32)(\      HFIELD_SHIFT(HMCBSP_RCR_RWDREVRS,rwdrevrs)|\      HFIELD_SHIFT(HMCBSP_RCR_RWDLEN1,rwdlen1)|\      HFIELD_SHIFT(HMCBSP_RCR_RFRLEN1,rfrlen1)|\      HFIELD_SHIFT(HMCBSP_RCR_RPHASE2,rphase2)|\      HFIELD_SHIFT(HMCBSP_RCR_RDATDLY,rdatdly)|\      HFIELD_SHIFT(HMCBSP_RCR_RFIG,rfig)|\      HFIELD_SHIFT(HMCBSP_RCR_RCOMPAND,rcompand)|\      HFIELD_SHIFT(HMCBSP_RCR_RWDLEN2,rwdlen2)|\      HFIELD_SHIFT(HMCBSP_RCR_RFRLEN2,rfrlen2)|\      HFIELD_SHIFT(HMCBSP_RCR_RPHASE,rphase)\    ) \  )  #define MCBSP_MK_XCR(xwdrevrs,xwdlen1,xfrlen1,xphase2,xdatdly,xfig,\    xcompand,xwdlen2,xfrlen2,xphase) ((Uint32)(\      HFIELD_SHIFT(HMCBSP_XCR_XWDREVRS,xwdrevrs)|\      HFIELD_SHIFT(HMCBSP_XCR_XWDLEN1,xwdlen1)|\      HFIELD_SHIFT(HMCBSP_XCR_XFRLEN1,xfrlen1)|\      HFIELD_SHIFT(HMCBSP_XCR_XPHASE2,xphase2)|\      HFIELD_SHIFT(HMCBSP_XCR_XDATDLY,xdatdly)|\      HFIELD_SHIFT(HMCBSP_XCR_XFIG,xfig)|\      HFIELD_SHIFT(HMCBSP_XCR_XCOMPAND,xcompand)|\      HFIELD_SHIFT(HMCBSP_XCR_XWDLEN2,xwdlen2)|\      HFIELD_SHIFT(HMCBSP_XCR_XFRLEN2,xfrlen2)|\      HFIELD_SHIFT(HMCBSP_XCR_XPHASE,xphase)\    ) \  )  /* make SRGR register value based on symbolic constants */  #define MCBSP_MK_SRGR(clkgdv,fwid,fper,fsgm,clksm,clksp,gsync) (\    (Uint32)(\      HFIELD_SHIFT(HMCBSP_SRGR_CLKGDV,clkgdv)|\      HFIELD_SHIFT(HMCBSP_SRGR_FWID,fwid)|\      HFIELD_SHIFT(HMCBSP_SRGR_FPER,fper)|\      HFIELD_SHIFT(HMCBSP_SRGR_FSGM,fsgm)|\      HFIELD_SHIFT(HMCBSP_SRGR_CLKSM,clksm)|\      HFIELD_SHIFT(HMCBSP_SRGR_CLKSP,clksp)|\      HFIELD_SHIFT(HMCBSP_SRGR_GSYNC,gsync)\    )\  )    #define MCBSP_MK_MCR(rmcm,rpablk,rpbblk,xmcm,xpablk,xpbblk)\    ((Uint32)(\      HFIELD_SHIFT(HMCBSP_MCR_RMCM,rmcm)|\      HFIELD_SHIFT(HMCBSP_MCR_RPABLK,rpablk)|\      HFIELD_SHIFT(HMCBSP_MCR_RPBBLK,rpbblk)|\      HFIELD_SHIFT(HMCBSP_MCR_XMCM,xmcm)|\      HFIELD_SHIFT(HMCBSP_MCR_XPABLK,xpablk)|\      HFIELD_SHIFT(HMCBSP_MCR_XPBBLK,xpbblk)\    )\  )    #define MCBSP_MK_RCER(rcea,rceb) (\    (Uint32)(\      (((Uint32)(rcea))&0x0000FFFF)|\      ((((Uint32)(rceb))<<16)&0xFFFF0000)\    )\  )    #define MCBSP_MK_XCER(xcea,xceb) (\    (Uint32)(\      (((Uint32)(xcea))&0x0000FFFF)|\      ((((Uint32)(xceb))<<16)&0xFFFF0000)\      )\  )  #define MCBSP_MK_PCR(clkrp,clkxp,fsrp,fsxp,dxstat,clksstat,clkrm,clkxm,\    fsrm,fsxm,rioen,xioen) ((Uint32)(\      HFIELD_SHIFT(HMCBSP_PCR_CLKRP,clkrp)|\      HFIELD_SHIFT(HMCBSP_PCR_CLKXP,clkxp)|\      HFIELD_SHIFT(HMCBSP_PCR_FSRP,fsrp)|\      HFIELD_SHIFT(HMCBSP_PCR_FSXP,fsxp)|\      HFIELD_SHIFT(HMCBSP_PCR_DXSTAT,dxstat)|\      HFIELD_SHIFT(HMCBSP_PCR_CLKSSTAT,clksstat)|\      HFIELD_SHIFT(HMCBSP_PCR_CLKRM,clkrm)|\      HFIELD_SHIFT(HMCBSP_PCR_CLKXM,clkxm)|\      HFIELD_SHIFT(HMCBSP_PCR_FSRM,fsrm)|\      HFIELD_SHIFT(HMCBSP_PCR_FSXM,fsxm)|\      HFIELD_SHIFT(HMCBSP_PCR_RIOEN,rioen)|\      HFIELD_SHIFT(HMCBSP_PCR_XIOEN,xioen)\    )\  )#endif /* MCBSP_SUPPORT */#if (PWR_SUPPORT)  #define PWR_MODE             PWR_Mode       //#define PWR_Init             PWR_init       #define PWR_Init()   #define PWR_PowerDown        PWR_powerDown      #define PWR_ConfigB          PWR_configArgs  #define PWR_MK_PDCTL(dma,emif,mcbsp0,mcbsp1,mcbsp2) ((Uint32)( \      HFIELD_SHIFT(HPWR_PDCTL_DMA,dma)|\      HFIELD_SHIFT(HPWR_PDCTL_EMIF,emif)|\      HFIELD_SHIFT(HPWR_PDCTL_MCBSP0,mcbsp0)|\      HFIELD_SHIFT(HPWR_PDCTL_MCBSP1,mcbsp1)|\      HFIELD_SHIFT(HPWR_PDCTL_MCBSP2,mcbsp2)\    )\  )#endif /* PWR_SUPPORT */#if (1)  #define UINT8                Uint8     #define UINT16               Uint16     #define UINT32               Uint32     #define UINT40               Uint40     #define INT8                 Int8     #define INT16                Int16     #define INT32                Int32     #define INT40                Int40     #define BOOL                 int  #define HANDLE               Handle   #endif#if (TIMER_SUPPORT)  #define TIMER_PRIVATE_OBJ    TIMER_PrivateObj         #define TIMER_HANDLE         TIMER_Handle         #define TIMER_CONFIG         TIMER_Config         #define TIMER_HDEV0          _TIMER_hDev0         #define TIMER_HDEV1          _TIMER_hDev1         #define TIMER_Reset          TIMER_reset         #define TIMER_Open           TIMER_open         #define TIMER_Close          TIMER_close         #define TIMER_ConfigA        TIMER_config  #define TIMER_ConfigB        TIMER_configArgs  //#define TIMER_Init           TIMER_init         #define TIMER_Init()  #define TIMER_GetEventId     TIMER_getEventId         #define TIMER_Start          TIMER_start         #define TIMER_Pause          TIMER_pause         #define TIMER_Resume         TIMER_resume         #define TIMER_GetPeriod      TIMER_getPeriod         #define TIMER_SetPeriod      TIMER_setPeriod         #define TIMER_GetCount       TIMER_getCount         #define TIMER_SetCount       TIMER_setCount         #define TIMER_GetDatin       TIMER_getDatIn         #define TIMER_SetDatout      TIMER_setDatOut         #define TIMER_GetTstat       TIMER_getTStat         /* make CTL register value based on symbolic constants */  #define TIMER_MK_CTL(func,invout,datout,pwid,go,hld,cp,clksrc,invinp)\    ((Uint32)( \      HFIELD_SHIFT(HTIMER_CTL_FUNC,func)|\      HFIELD_SHIFT(HTIMER_CTL_INVOUT,invout)|\      HFIELD_SHIFT(HTIMER_CTL_DATOUT,datout)|\      HFIELD_SHIFT(HTIMER_CTL_PWID,pwid)|\      HFIELD_SHIFT(HTIMER_CTL_GO,go)|\      HFIELD_SHIFT(HTIMER_CTL_HLD,hld)|\      HFIELD_SHIFT(HTIMER_CTL_CP,cp)|\      HFIELD_SHIFT(HTIMER_CTL_CLKSRC,clksrc)|\      HFIELD_SHIFT(HTIMER_CTL_INVINP,invinp)\    ) \  )#endif /* TIMER_SUPPORT *//******************************************************************************\* global typedef declarations\******************************************************************************/#if (DMA_SUPPORT&&0)  typedef enum {    DMA_GBL_ADDRRLD = 0x00,    DMA_GBL_INDEX   = 0x04,    DMA_GBL_CNTRLD  = 0x08,    DMA_GBL_SPLIT   = 0x0C  } DMA_Gbl;#endif /* DMA_SUPPORT */#if (EMIF_SUPPORT)/* device configuration structure */typedef struct {  UINT32 gblctl;  UINT32 ce0ctl;  UINT32 ce1ctl;  UINT32 ce2ctl;  UINT32 ce3ctl;  UINT32 sdctl;  UINT32 sdtim;  UINT32 sdext;} EMIF_CONFIG;#endif /* EMIF_SUPPORT *//******************************************************************************\* global variable declarations\******************************************************************************/#if (DMA_SUPPORT&&0)  extern far Uint32 _DMA_gblRegTbl[_DMA_GBLREG_CNT];#endif /* DMA_SUPPORT *//******************************************************************************\* global function declarations\******************************************************************************/#if (DMA_SUPPORT&&0)  CSLAPI Uint32 DMA_allocGlobalReg(DMA_Gbl regType, Uint32 initVal);  CSLAPI void   DMA_freeGlobalReg(Uint32 regId);#endif /* DMA_SUPPORT */  #if (EMIF_SUPPORT)  CSLAPI void EMIF_ConfigA(EMIF_CONFIG *Config);  CSLAPI void EMIF_ConfigB(UINT32 gblctl, UINT32 ce0ctl, UINT32 ce1ctl,    UINT32 ce2ctl, UINT32 ce3ctl, UINT32 sdctl, UINT32 sdtim, UINT32 sdext);#endif/******************************************************************************\* inline function declarations\******************************************************************************/#if (DMA_SUPPORT&&0)  IDECL Uint32 DMA_getGlobalRegAddr(Uint32 regId);  IDECL Uint32 DMA_getGlobalReg(Uint32 regId);  IDECL void   DMA_setGlobalReg(Uint32 regId, Uint32 val);#endif /* DMA_SUPPORT *//******************************************************************************\* inline function definitions\******************************************************************************/#ifdef USEDEFS#if (DMA_SUPPORT&&0)/*----------------------------------------------------------------------------*/IDEF Uint32 DMA_getGlobalRegAddr(Uint32 regId) {  return _DMA_gblRegTbl[regId&_DMA_GBLREG_MASK];}/*----------------------------------------------------------------------------*/IDEF Uint32 DMA_getGlobalReg(Uint32 regId) {  return REG32(_DMA_gblRegTbl[regId&_DMA_GBLREG_MASK]);}/*----------------------------------------------------------------------------*/IDEF void DMA_setGlobalReg(Uint32 regId, Uint32 val) {  REG32(_DMA_gblRegTbl[regId&_DMA_GBLREG_MASK])=val;}/*----------------------------------------------------------------------------*/#endif /* DMA_SUPPORT *//*----------------------------------------------------------------------------*/#endif /* USEDEFS */#endif /* _CSL_LEGACY_H_ *//******************************************************************************\* End of csl_legacy.h\******************************************************************************/