/******************************************************************************\*           Copyright (C) 1999-2000 Texas Instruments Incorporated.*                           All Rights Reserved*------------------------------------------------------------------------------* FILENAME...... csl_i2chal.h* DATE CREATED.. 10/02/2001 * .............. 10/11/2001    first draft completed* LAST MODIFIED. 11/19/2001    register renaming *                11/09/2001    update bit field names *                07/02/2003    update to latest spec.*------------------------------------------------------------------------------* REGISTERS** I2COAR0    - I2C0 Own Address register* I2COAR1    - I2C1 Own Address register* I2CIER0    - I2C0 Interrupt Mask/Status register* I2CIER1    - I2C1 Interrupt Mask/Status register* I2CSTR0    - I2C0 Interrupt Status register* I2CSTR1    - I2C1 Interrupt Status register* I2CCLKL0   - I2C0 Clock Divider Low register* I2CCLKL1   - I2C1 Clock Divider Low register* I2CCLKH0   - I2C0 Clock Divider High register* I2CCLKH1   - I2C1 Clock Divider High register* I2CCNT0    - I2C0 Data Count register* I2CCNT1    - I2C1 Data Count register* I2CDRR0    - I2C0 Data Receive register* I2CDRR1    - I2C1 Data Receive register* I2CSAR0    - I2C0 Slave Address register* I2CSAR1    - I2C1 Slave Address register* I2CDXR0    - I2C0 Data Transmit register* I2CDXR1    - I2C1 Data Transmit register* I2CMDR0    - I2C0 Mode register* I2CMDR1    - I2C1 Mode register* I2CISRC0    - I2C0 Interrupt Vector register* I2CISRC1    - I2C1 Interrupt Vector register* I2CEMDR0   - I2C0 Extended Mode register(1)* I2CEMDR1   - I2C1 Extended Mode register(1)* I2CPSC0    - I2C0 Prescaler register* I2CPSC1    - I2C1 Prescaler register* I2CPID10   - I2C0 Peripheral ID register 1(1)* I2CPID11   - I2C1 Peripheral ID register 1(1)* I2CPID20   - I2C0 Peripheral ID register 2(1)* I2CPID21   - I2C1 Peripheral ID register 2(1)* I2CPFUNC0  - I2C0 Peripheral Functional register(1)* I2CPFUNC1  - I2C1 Peripheral Functional register(1)* I2CPDIR0   - I2C0 Pin Direction register(1)* I2CPDIR1   - I2C1 Pin Direction register(1)* I2CPDIN0   - I2C0 Pin Data In register(1)* I2CPDIN1   - I2C1 Pin Data In register(1)* I2CPDOUT0  - I2C0 Pin Data Out register(1)* I2CPDOUT1  - I2C1 Pin Data Out register(1)* I2CPDSET0  - I2C0 Pin Data Set register(1)* I2CPDSET1  - I2C1 Pin Data Set register(1)* I2CPDCLR0  - I2C0 Pin Data Clear register(1)* I2CPDCLR1  - I2C1 Pin Data Clear register(1)** (1) For C6418/C6413/C6410 only\******************************************************************************/#ifndef _CSL_I2CHAL_H_#define _CSL_I2CHAL_H_#include <csl_stdinc.h>#include <csl_chip.h>#if (I2C_SUPPORT)/******************************************************************************\* MISC section\******************************************************************************/#if (CHIP_6713 || CHIP_DA610 || CHIP_6418 || CHIP_6413 || CHIP_6410)  #define _I2C_PORT_CNT        2  #define _I2C_BASE_PORT0      0x01B40000u  #define _I2C_BASE_PORT1      0x01B44000u#endif#if (CHIP_DM642 | CHIP_6412)  #define _I2C_PORT_CNT        1  #define _I2C_BASE_PORT0      0x01B40000u#endif /******************************************************************************\* module level register/field access macros\******************************************************************************/  /* ----------------- */  /* FIELD MAKE MACROS */  /* ----------------- */  #define I2C_FMK(REG,FIELD,x)\    _PER_FMK(I2C,##REG,##FIELD,x)  #define I2C_FMKS(REG,FIELD,SYM)\    _PER_FMKS(I2C,##REG,##FIELD,##SYM)  /* -------------------------------- */  /* RAW REGISTER/FIELD ACCESS MACROS */  /* -------------------------------- */  #define I2C_ADDR(REG)\    _I2C_##REG##_ADDR  #define I2C_RGET(REG)\    _PER_RGET(_I2C_##REG##_ADDR,I2C,##REG)  #define I2C_RSET(REG,x)\    _PER_RSET(_I2C_##REG##_ADDR,I2C,##REG,x)  #define I2C_FGET(REG,FIELD)\    _I2C_##REG##_FGET(##FIELD)  #define I2C_FSET(REG,FIELD,x)\    _I2C_##REG##_FSET(##FIELD,##x)  #define I2C_FSETS(REG,FIELD,SYM)\    _I2C_##REG##_FSETS(##FIELD,##SYM)  /* ------------------------------------------ */  /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */  /* ------------------------------------------ */  #define I2C_RGETA(addr,REG)\    _PER_RGET(addr,I2C,##REG)  #define I2C_RSETA(addr,REG,x)\    _PER_RSET(addr,I2C,##REG,x)  #define I2C_FGETA(addr,REG,FIELD)\    _PER_FGET(addr,I2C,##REG,##FIELD)  #define I2C_FSETA(addr,REG,FIELD,x)\    _PER_FSET(addr,I2C,##REG,##FIELD,x)  #define I2C_FSETSA(addr,REG,FIELD,SYM)\    _PER_FSETS(addr,I2C,##REG,##FIELD,##SYM)  /* ----------------------------------------- */  /* HANDLE BASED REGISTER/FIELD ACCESS MACROS */  /* ----------------------------------------- */  #define I2C_ADDRH(h,REG)\    (Uint32)(&((h)->baseAddr[_I2C_##REG##_OFFSET]))  #define I2C_RGETH(h,REG)\    I2C_RGETA(I2C_ADDRH(h,##REG),##REG)  #define I2C_RSETH(h,REG,x)\    I2C_RSETA(I2C_ADDRH(h,##REG),##REG,x)  #define I2C_FGETH(h,REG,FIELD)\    I2C_FGETA(I2C_ADDRH(h,##REG),##REG,##FIELD)  #define I2C_FSETH(h,REG,FIELD,x)\    I2C_FSETA(I2C_ADDRH(h,##REG),##REG,##FIELD,x)  #define I2C_FSETSH(h,REG,FIELD,SYM)\    I2C_FSETSA(I2C_ADDRH(h,##REG),##REG,##FIELD,##SYM)/******************************************************************************\*  ___________________* |                   |* |  I 2 C O A R      |* |___________________|** I2COAR0    - I2C0 Own Address register* I2COAR1    - I2C1 Own Address register** FIELDS (msb -> lsb)* (rw) A*\******************************************************************************/  #define _I2C_I2COAR_OFFSET           0  #define _I2C_I2COAR0_ADDR            0x01B40000  #define _I2C_I2COAR1_ADDR            0x01B44000  #define _I2C_I2COAR_A_MASK          0x000003FFu   #define _I2C_I2COAR_A_SHIFT         0x00000000u  #define  I2C_I2COAR_A_DEFAULT       0x00000000u  #define  I2C_I2COAR_A_OF(x)         _VALUEOF(x)  #define  I2C_I2COAR_OF(x)             _VALUEOF(x)  #define I2C_I2COAR_DEFAULT (Uint32)(\     _PER_FDEFAULT(I2C,I2COAR,A)\  )  #define I2C_I2COAR_RMK(a) (Uint32)(\     _PER_FMK(I2C,I2COAR,A,a)\  )     #define _I2C_I2COAR_FGET(N,FIELD)\    _PER_FGET(_I2C_I2COAR##N##_ADDR,I2C,I2COAR,##FIELD)  #define _I2C_I2COAR_FSET(N,FIELD,field)\    _PER_FSET(_I2C_I2COAR##N##_ADDR,I2C,I2COAR,##FIELD,field)  #define _I2C_I2COAR_FSETS(N,FIELD,SYM)\    _PER_FSETS(_I2C_I2COAR##N##_ADDR,I2C,I2COAR,##FIELD,##SYM)  #define _I2C_I2COAR0_FGET(FIELD) _I2C_I2COAR_FGET(0,##FIELD)  #define _I2C_I2COAR1_FGET(FIELD) _I2C_I2COAR_FGET(1,##FIELD)  #define _I2C_I2COAR0_FSET(FIELD,f) _I2C_I2COAR_FSET(0,##FIELD,f)  #define _I2C_I2COAR1_FSET(FIELD,f) _I2C_I2COAR_FSET(1,##FIELD,f)  #define _I2C_I2COAR0_FSETS(FIELD,SYM) _I2C_I2COAR_FSETS(0,##FIELD,##SYM)  #define _I2C_I2COAR1_FSETS(FIELD,SYM) _I2C_I2COAR_FSETS(1,##FIELD,##SYM)/******************************************************************************\*  (Keeping the old definitions for backward compatibility)*  ___________________* |                   |* |  I 2 C I M R      |* |___________________|** I2CIMR0    - I2C0 Interrupt Mask/Status register* I2CIMR1    - I2C1 Interrupt Mask/Status register** FIELDS (msb -> lsb)* (rw) ICXRDY* (rw) ICRRDY* (rw) ARDY* (rw) NACK* (rw) AL\******************************************************************************/#if (!(CHIP_6410 | CHIP_6413 | CHIP_6418))  #define _I2C_I2CIMR_OFFSET           1  #define _I2C_I2CIMR0_ADDR            0x01B40004  #define _I2C_I2CIMR1_ADDR            0x01B44004  #define _I2C_I2CIMR_ICXRDY_MASK          0x00000010u  #define _I2C_I2CIMR_ICXRDY_SHIFT         0x00000004u  #define  I2C_I2CIMR_ICXRDY_DEFAULT       0x00000000u  #define  I2C_I2CIMR_ICXRDY_OF(x)         _VALUEOF(x)  #define  I2C_I2CIMR_ICXRDY_MSK           0x00000000u  #define  I2C_I2CIMR_ICXRDY_UNMSK         0x00000001u  #define _I2C_I2CIMR_ICRRDY_MASK          0x00000008u  #define _I2C_I2CIMR_ICRRDY_SHIFT         0x00000003u  #define  I2C_I2CIMR_ICRRDY_DEFAULT       0x00000000u  #define  I2C_I2CIMR_ICRRDY_OF(x)         _VALUEOF(x)  #define  I2C_I2CIMR_ICRRDY_MSK           0x00000000u  #define  I2C_I2CIMR_ICRRDY_UNMSK         0x00000001u  #define _I2C_I2CIMR_ARDY_MASK            0x00000004u  #define _I2C_I2CIMR_ARDY_SHIFT           0x00000002u  #define  I2C_I2CIMR_ARDY_DEFAULT         0x00000000u  #define  I2C_I2CIMR_ARDY_OF(x)           _VALUEOF(x)  #define  I2C_I2CIMR_ARDY_MSK             0x00000000u  #define  I2C_I2CIMR_ARDY_UNMSK           0x00000001u  #define _I2C_I2CIMR_NACK_MASK            0x00000002u  #define _I2C_I2CIMR_NACK_SHIFT           0x00000001u  #define  I2C_I2CIMR_NACK_DEFAULT         0x00000000u  #define  I2C_I2CIMR_NACK_OF(x)           _VALUEOF(x)  #define  I2C_I2CIMR_NACK_MSK             0x00000000u  #define  I2C_I2CIMR_NACK_UNMSK           0x00000001u  #define _I2C_I2CIMR_AL_MASK              0x00000001u  #define _I2C_I2CIMR_AL_SHIFT             0x00000000u  #define  I2C_I2CIMR_AL_DEFAULT           0x00000000u  #define  I2C_I2CIMR_AL_OF(x)             _VALUEOF(x)  #define  I2C_I2CIMR_AL_MSK               0x00000000u  #define  I2C_I2CIMR_AL_UNMSK             0x00000001u  #define  I2C_I2CIMR_OF(x)                _VALUEOF(x)  #define I2C_I2CIMR_DEFAULT (Uint32)(\      _PER_FDEFAULT(I2C,I2CIMR,ICXRDY)\     |_PER_FDEFAULT(I2C,I2CIMR,ICRRDY)\     |_PER_FDEFAULT(I2C,I2CIMR,ARDY)\     |_PER_FDEFAULT(I2C,I2CIMR,NACK)\     |_PER_FDEFAULT(I2C,I2CIMR,AL)\  )  #define I2C_I2CIMR_RMK(icxrdy,icrrdy,ardy,nack,al) (Uint32)(\      _PER_FMK(I2C,I2CIMR,ICXRDY,icxrdy)\     |_PER_FMK(I2C,I2CIMR,ICRRDY,icrrdy)\     |_PER_FMK(I2C,I2CIMR,ARDY,ardy)\     |_PER_FMK(I2C,I2CIMR,NACK,nack)\     |_PER_FMK(I2C,I2CIMR,AL,al)\  )       #define _I2C_I2CIMR_FGET(N,FIELD)\    _PER_FGET(_I2C_I2CIMR##N##_ADDR,I2C,I2CIMR,##FIELD)  #define _I2C_I2CIMR_FSET(N,FIELD,field)\    _PER_FSET(_I2C_I2CIMR##N##_ADDR,I2C,I2CIMR,##FIELD,field)  #define _I2C_I2CIMR_FSETS(N,FIELD,SYM)\    _PER_FSETS(_I2C_I2CIMR##N##_ADDR,I2C,I2CIMR,##FIELD,##SYM)  #define _I2C_I2CIMR0_FGET(FIELD) _I2C_I2CIMR_FGET(0,##FIELD)  #define _I2C_I2CIMR1_FGET(FIELD) _I2C_I2CIMR_FGET(1,##FIELD)  #define _I2C_I2CIMR0_FSET(FIELD,f) _I2C_I2CIMR_FSET(0,##FIELD,f)  #define _I2C_I2CIMR1_FSET(FIELD,f) _I2C_I2CIMR_FSET(1,##FIELD,f)  #define _I2C_I2CIMR0_FSETS(FIELD,SYM) _I2C_I2CIMR_FSETS(0,##FIELD,##SYM)  #define _I2C_I2CIMR1_FSETS(FIELD,SYM) _I2C_I2CIMR_FSETS(1,##FIELD,##SYM)#endif/******************************************************************************\*  ___________________* |                   |* |  I 2 C I E R      |* |___________________|** I2CIER0    - I2C0 Interrupt Mask/Status register* I2CIER1    - I2C1 Interrupt Mask/Status register** FIELDS (msb -> lsb)* (rw) AAS(1)* (rw) SCD(1)* (rw) ICXRDY* (rw) ICRRDY* (rw) ARDY* (rw) NACK* (rw) AL**  (1) For  C6418/C6413/C6410 only\******************************************************************************/  #define _I2C_I2CIER_OFFSET           1  #define _I2C_I2CIER0_ADDR            0x01B40004  #define _I2C_I2CIER1_ADDR            0x01B44004#if (CHIP_6418 || CHIP_6413 || CHIP_6410)  #define _I2C_I2CIER_AAS_MASK             0x00000040u  #define _I2C_I2CIER_AAS_SHIFT            0x00000006u  #define  I2C_I2CIER_AAS_DEFAULT          0x00000000u  #define  I2C_I2CIER_AAS_OF(x)            _VALUEOF(x)  #define  I2C_I2CIER_AAS_MSK              0x00000000u  #define  I2C_I2CIER_AAS_UNMSK            0x00000001u  #define _I2C_I2CIER_SCD_MASK             0x00000020u  #define _I2C_I2CIER_SCD_SHIFT            0x00000005u  #define  I2C_I2CIER_SCD_DEFAULT          0x00000000u  #define  I2C_I2CIER_SCD_OF(x)            _VALUEOF(x)  #define  I2C_I2CIER_SCD_MSK              0x00000000u  #define  I2C_I2CIER_SCD_UNMSK            0x00000001u#endif  #define _I2C_I2CIER_ICXRDY_MASK          0x00000010u  #define _I2C_I2CIER_ICXRDY_SHIFT         0x00000004u  #define  I2C_I2CIER_ICXRDY_DEFAULT       0x00000000u  #define  I2C_I2CIER_ICXRDY_OF(x)         _VALUEOF(x)  #define  I2C_I2CIER_ICXRDY_MSK           0x00000000u  #define  I2C_I2CIER_ICXRDY_UNMSK         0x00000001u  #define _I2C_I2CIER_ICRRDY_MASK          0x00000008u  #define _I2C_I2CIER_ICRRDY_SHIFT         0x00000003u  #define  I2C_I2CIER_ICRRDY_DEFAULT       0x00000000u  #define  I2C_I2CIER_ICRRDY_OF(x)         _VALUEOF(x)  #define  I2C_I2CIER_ICRRDY_MSK           0x00000000u  #define  I2C_I2CIER_ICRRDY_UNMSK         0x00000001u