/*****************************************************************************\*           Copyright (C) 1999-2003 Texas Instruments Incorporated.*                           All Rights Reserved*------------------------------------------------------------------------------* FILENAME...... csl_emachal.h* DATE CREATED.. 02/04/2002* LAST MODIFIED. 03/05/2003*------------------------------------------------------------------------------* REGISTERS/PARAMETERS** TXIDVER           - TX Identification and Version Register* TXCONTROL         - TX Control Register* TXTEARDOWN        - TX Teardown Register* RXIDVER           - RX Identification and Version Register* RXCONTROL         - RX Control Register* RXTEARDOWN        - RX Teardown Register* RXMBPENABLE       - RX Mulicast/Bcast/Promisc Channel Enable Register* RXUNICASTSET      - RX Unicast Set Register* RXUNICASTCLEAR    - RX Unicast Clear Register* RXMAXLEN          - RX Maximum Length Register* RXBUFFEROFFSET    - RX Buffer Offset Register* RXFILTERLOWTHRESH - RX Filer Low Priority Packets Threshhold* RX0FLOWTHRESH     - RX Channel 0 Flow Control Threshhold* RX1FLOWTHRESH     - RX Channel 1 Flow Control Threshhold* RX2FLOWTHRESH     - RX Channel 2 Flow Control Threshhold* RX3FLOWTHRESH     - RX Channel 3 Flow Control Threshhold* RX4FLOWTHRESH     - RX Channel 4 Flow Control Threshhold* RX5FLOWTHRESH     - RX Channel 5 Flow Control Threshhold* RX6FLOWTHRESH     - RX Channel 6 Flow Control Threshhold* RX7FLOWTHRESH     - RX Channel 7 Flow Control Threshhold* RX0FREEBUFFER     - RX Channel 0 Free Buffer Count Register* RX1FREEBUFFER     - RX Channel 1 Free Buffer Count Register* RX2FREEBUFFER     - RX Channel 2 Free Buffer Count Register* RX3FREEBUFFER     - RX Channel 3 Free Buffer Count Register* RX4FREEBUFFER     - RX Channel 4 Free Buffer Count Register* RX5FREEBUFFER     - RX Channel 5 Free Buffer Count Register* RX6FREEBUFFER     - RX Channel 6 Free Buffer Count Register* RX7FREEBUFFER     - RX Channel 7 Free Buffer Count Register* MACCONTROL        - MAC Control Register* MACSTATUS         - MAC Status Register* EMCONTROL         - Emulation Control Register* TXINTSTATRAW      - TX Interrupt Status Register (Unmasked)* TXINTSTATMASKED   - TX Interrupt Status Register (Masked)* TXINTMASKSET      - TX Interrupt Mask Set Register* TXINTMASKCLEAR    - TX Interrupt Mask Clear Register* MACINVECTOR       - MAC Input Vector* MACEOIVECTOR      - MAC EOI Vector* RXINTSTATRAW      - RX Interrupt Status Register (Unmasked)* RXINTSTATMASKED   - RX Interrupt Status Register (Masked)* RXINTMASKSET      - RX Interrupt Mask Set Register* RXINTMASKCLEAR    - RX Interrupt Mask Clear Register* MACINTSTATRAW     - MAC Interrupt Status Register (Unmasked)* MACINTSTATMASKED  - MAC Interrupt Status Register (Masked)* MACINTMASKSET     - MAC Interrupt Mask Set Register* MACINTMASKCLEAR   - MAC Interrupt Mask Clear Register* MACADDRL0         - MAC Address Channel 0 Lower Byte Register* MACADDRL1         - MAC Address Channel 1 Lower Byte Register* MACADDRL2         - MAC Address Channel 2 Lower Byte Register* MACADDRL3         - MAC Address Channel 3 Lower Byte Register* MACADDRL4         - MAC Address Channel 4 Lower Byte Register* MACADDRL5         - MAC Address Channel 5 Lower Byte Register* MACADDRL6         - MAC Address Channel 6 Lower Byte Register* MACADDRL7         - MAC Address Channel 7 Lower Byte Register* MACADDRM          - MAC Address Middle Byte Register* MACADDRH          - MAC Address High Bytes Register* MACHASH1          - MAC Address Hash 1 Register* MACHASH2          - MAC Address Hash 2 Register* BOFFTEST          - Backoff Test Register* TPACETEST         - Transmit Pacing Test Register* RXPAUSE           - Receive Pause Timer Register* TXPAUSE           - Transmit Pause Timer Register* RXGOODFRAMES      - Number of Good Frames Received* RXBCASTFRAMES     - Number of Good Broadcast Frames Received* RXMCASTFRAMES     - Number of Good Multicast Frames Received* RXPAUSEFRAMES     - Number of PauseRX Frames Received* RXCRCERRORS       - Number of Frames Received with CRC Errors* RXALIGNCODEERRORS - Number of Frames Received with Alignment/Code Errors* RXOVERSIZED       - Number of Oversized Frames Received* RXJABBER          - Number of Jabber Frames Received* RXUNDERSIZED      - Number of Undersized Frames Received* RXFRAGMENTS       - Number of RX Frame Fragments Received* RXFILTERED        - Number of RX Frames Filtered Based on Address* RXQOSFILTERED     - Number of RX Frames Filtered Based on QoS Filtering* RXOCTETS          - Total Number of Received Bytes in Good Frames* TXGOODFRAMES      - Number of Good Frames Sent* TXBCASTFRAMES     - Number of Good Broadcast Frames Sent* TXMCASTFRAMES     - Number of Good Multicast Frames Sent* TXPAUSEFRAMES     - Number of PauseTX Frames Sent* TXDEFERRED        - Number of Frames Where Transmission was Deferred* TXCOLLISION       - Total Number of Frames Sent That Experienced a Collision* TXSINGLECOLL      - Number of Frames Sent with Exactly One Collision* TXMULTICOLL       - Number of Frames Sent with Multiple Colisions* TXEXCESSIVECOLL   - Number of TX Frames Lost Due to Excessive Collisions* TXLATECOLL        - Number of TX Frames Lost Due to a Late Collision* TXUNDERRUN        - Number of TX Frames Lost with Transmit Underrun Error* TXCARRIERSLOSS    - Numebr of TX Frames Lost Due to Carrier Sense Loss* TXOCTETS          - Total Nu,ber of Transmitted Bytes in Good Frames* FRAME64           - Total TX & RX Frames with Octet Size of 64* FRAME65T127       - Total TX & RX Frames with Octet Size of 65 to 127* FRAME128T255      - Total TX & RX Frames with Octet Size of 128 to 255* FRAME256T511      - Total TX & RX Frames with Octet Size of 256 to 511* FRAME512T1023     - Total TX & RX Frames with Octet Size of 512 to 1023* FRAME1024TUP      - Total TX & RX Frames with Octet Size of 1024 or above* NETOCTETS         - Sum of all Octets Sent or Received on the Network* RXSOFOVERRUNS     - Total RX Start of Frame Overruns (FIFO or DMA)* RXMOFOVERRUNS     - Total RX Middle of Frame Overruns (FIFO or DMA)* RXDMAOVERRUNS     - Total RX DMA Overruns* TX0HDP            - TX Channel 0 DMA Head Descriptor Pointer Register* TX1HDP            - TX Channel 1 DMA Head Descriptor Pointer Register* TX2HDP            - TX Channel 2 DMA Head Descriptor Pointer Register* TX3HDP            - TX Channel 3 DMA Head Descriptor Pointer Register* TX4HDP            - TX Channel 4 DMA Head Descriptor Pointer Register* TX5HDP            - TX Channel 5 DMA Head Descriptor Pointer Register* TX6HDP            - TX Channel 6 DMA Head Descriptor Pointer Register* TX7HDP            - TX Channel 7 DMA Head Descriptor Pointer Register* RX0HDP            - RX Channel 0 DMA Head Descriptor Pointer Register* RX1HDP            - RX Channel 1 DMA Head Descriptor Pointer Register* RX2HDP            - RX Channel 2 DMA Head Descriptor Pointer Register* RX3HDP            - RX Channel 3 DMA Head Descriptor Pointer Register* RX4HDP            - RX Channel 4 DMA Head Descriptor Pointer Register* RX5HDP            - RX Channel 5 DMA Head Descriptor Pointer Register* RX6HDP            - RX Channel 6 DMA Head Descriptor Pointer Register* RX7HDP            - RX Channel 7 DMA Head Descriptor Pointer Register* TX0INTACK         - TX Channel 0 Interrupt Acknowledge Register* TX1INTACK         - TX Channel 1 Interrupt Acknowledge Register* TX2INTACK         - TX Channel 2 Interrupt Acknowledge Register* TX3INTACK         - TX Channel 3 Interrupt Acknowledge Register* TX4INTACK         - TX Channel 4 Interrupt Acknowledge Register* TX5INTACK         - TX Channel 5 Interrupt Acknowledge Register* TX6INTACK         - TX Channel 6 Interrupt Acknowledge Register* TX7INTACK         - TX Channel 7 Interrupt Acknowledge Register* RX0INTACK         - RX Channel 0 Interrupt Acknowledge Register* RX1INTACK         - RX Channel 1 Interrupt Acknowledge Register* RX2INTACK         - RX Channel 2 Interrupt Acknowledge Register* RX3INTACK         - RX Channel 3 Interrupt Acknowledge Register* RX4INTACK         - RX Channel 4 Interrupt Acknowledge Register* RX5INTACK         - RX Channel 5 Interrupt Acknowledge Register* RX6INTACK         - RX Channel 6 Interrupt Acknowledge Register* RX7INTACK         - RX Channel 7 Interrupt Acknowledge Register*** WRAPPER REGISTERS** INTCTL            - Interrupt control register*** DESCRIPTOR FIELDS** DSC_NEXTDSC       - Pointer to Next Descriptor* DSC_BUFFER        - Pointer to Buffer* DSC_OFFLEN        - Buffer Offset and Length* DSC_STATUS        - Packet Status**\******************************************************************************/#ifndef _CSL_EMACHAL_H#define _CSL_EMACHAL_H_#include <csl_stdinc.h>#include <csl_chip.h>#if (EMAC_SUPPORT)/******************************************************************************\* EMAC Register section\******************************************************************************/#define _EMAC_BASE_ADDR             0x01c80000u/* ----------------- *//* FIELD MAKE MACROS *//* ----------------- *//* User Supplied Value */#define EMAC_FMK(REG,FIELD,x)\  ((x<<_EMAC_##REG##_##FIELD##_SHIFT)&_EMAC_##REG##_##FIELD##_MASK)/* Symbolic Value Name */#define EMAC_FMKS(REG,FIELD,SYM)\  ((EMAC_##REG##_##FIELD##_##SYM<<_EMAC_##REG##_##FIELD##_SHIFT)\  &_EMAC_##REG##_##FIELD##_MASK)/* Channel Flag */#define EMAC_FMKCHF(CHANNEL)    (1u<<(CHANNEL))/* -------------------------------- *//* RAW REGISTER/FIELD ACCESS MACROS *//* -------------------------------- */#define EMAC_ADDR(REG)\    ((volatile Uint32 *)_EMAC_##REG##_ADDR)#define EMAC_REG(REG)\    *(volatile Uint32*)(_EMAC_##REG##_ADDR)/* Standard Registers */#define EMAC_RGET(REG)\    (*(volatile Uint32*)(_EMAC_##REG##_ADDR))#define EMAC_RSET(REG,x)\    (*(volatile Uint32*)(_EMAC_##REG##_ADDR)=(x))#define EMAC_FGET(REG,FIELD)\    ((EMAC_RGET(REG)&_EMAC_##REG##_##FIELD##_MASK)\    >>_EMAC_##REG##_##FIELD##_SHIFT)#define EMAC_FSET(REG,FIELD,x)\    EMAC_RSET(REG,(EMAC_RGET(REG)&~_EMAC_##REG##_##FIELD##_MASK)|\    EMAC_FMK(REG,FIELD,x))#define EMAC_FSETS(REG,FIELD,SYM)\    EMAC_RSET(REG,(EMAC_RGET(REG)&~_EMAC_##REG##_##FIELD##_MASK)|\    EMAC_FMKS(REG,FIELD,SYM))/* Index Based Registers */#define EMAC_RGETI(REGBASE,IDX)\    (*(volatile Uint32*)(_EMAC_##REGBASE##_BASEADDR+((IDX)*sizeof(Uint32 *))))#define EMAC_RSETI(REGBASE,IDX,x)\    (*(volatile Uint32*)(_EMAC_##REGBASE##_BASEADDR+((IDX)*sizeof(Uint32 *)))=(x))#define EMAC_FGETI(REGBASE,IDX,FIELD)\    ((EMAC_RGETI(REGBASE,IDX)&_EMAC_##REGBASE##_##FIELD##_MASK)\    >>_EMAC_##REGBASE##_##FIELD##_SHIFT)#define EMAC_FSETI(REGBASE,IDX,FIELD,x)\    EMAC_RSETI(REGBASE,IDX,(EMAC_RGETI(REGBASE,IDX)&\    ~_EMAC_##REGBASE##_##FIELD##_MASK)|EMAC_FMK(REGBASE,FIELD,x))#define EMAC_FSETSI(REGBASE,IDX,FIELD,SYM)\    EMAC_RSETI(REGBASE,IDX,(EMAC_RGETI(REGBASE,IDX)&\    ~_EMAC_##REGBASE##_##FIELD##_MASK)|EMAC_FMKS(REGBASE,FIELD,SYM))/******************************************************************************\* EMAC Descriptor section\******************************************************************************/#define _EMAC_DSC_BASE_ADDR         0x01c81000u/* EMAC Descriptor Size and Element Count */#define _EMAC_DSC_SIZE              4096#define _EMAC_DSC_ENTRY_SIZE        16#define _EDMA_DSC_ENTRY_COUNT       (_EMAC_DSC_SIZE/_EMAC_DSC_ENTRY_SIZE)/*// EMAC Descriptor//// The following is the format of a single buffer descriptor// on the EMAC.*/typedef struct _EMAC_Desc {  struct _EMAC_Desc *pNext;     /* Pointer to next descriptor in chain */  Uint8             *pBuffer;   /* Pointer to data buffer              */  Uint32            BufOffLen;  /* Buffer Offset(MSW) and Length(LSW)  */  Uint32            PktFlgLen;  /* Packet Flags(MSW) and Length(LSW)   */} EMAC_Desc;/* ------------------------ *//* DESCRIPTOR ACCESS MACROS *//* ------------------------ *//* Packet Flags */#define EMAC_DSC_FLAG_SOP                       0x80000000u#define EMAC_DSC_FLAG_EOP                       0x40000000u#define EMAC_DSC_FLAG_OWNER                     0x20000000u#define EMAC_DSC_FLAG_EOQ                       0x10000000u#define EMAC_DSC_FLAG_TDOWNCMPLT                0x08000000u#define EMAC_DSC_FLAG_PASSCRC                   0x04000000u#define EMAC_DSC_FLAG_JABBER                    0x02000000u#define EMAC_DSC_FLAG_OVERSIZE                  0x01000000u#define EMAC_DSC_FLAG_FRAGMENT                  0x00800000u#define EMAC_DSC_FLAG_UNDERSIZED                0x00400000u#define EMAC_DSC_FLAG_CONTROL                   0x00200000u#define EMAC_DSC_FLAG_OVERRUN                   0x00100000u#define EMAC_DSC_FLAG_CODEERROR                 0x00080000u#define EMAC_DSC_FLAG_ALIGNERROR                0x00040000u#define EMAC_DSC_FLAG_CRCERROR                  0x00020000u#define EMAC_DSC_FLAG_NOMATCH                   0x00010000u/******************************************************************************\* module level register/field access macros\******************************************************************************//******************************************************************************\* _____________________* |                   |* |  TXIDVER          |* |___________________|** TXIDVER           - TX Identification and Version Register** FIELDS (msb -> lsb)* (r)   TXIDENT* (r)   TXMAJORVER* (r)   TXMINORVER** MACROS SUPPORTED*  EMAC_FMK     y*  EMAC_FMKS    .*  EMAC_FMKCHF  .*  EMAC_ADDR    y*  EMAC_REG     y*  EMAC_RGET    y*  EMAC_RSET    y*  EMAC_FGET    y*  EMAC_FSET    y*  EMAC_FSETS   .*  EMAC_RGETI   .*  EMAC_RSETI   .*  EMAC_FGETI   .*  EMAC_FSETI   .*  EMAC_FSETSI  .*\******************************************************************************/#define _EMAC_TXIDVER_ADDR                      (_EMAC_BASE_ADDR+0x0000u)#define EMAC_TXIDVER                            EMAC_REG(TXIDVER)#define _EMAC_TXIDVER_TXIDENT_MASK              0xFFFF0000u#define _EMAC_TXIDVER_TXIDENT_SHIFT             16u#define  EMAC_TXIDVER_TXIDENT_DEFAULT           0x00000004u#define _EMAC_TXIDVER_TXMAJORVER_MASK           0x0000FF00u#define _EMAC_TXIDVER_TXMAJORVER_SHIFT          8u#define  EMAC_TXIDVER_TXMAJORVER_DEFAULT        0x00000000u#define _EMAC_TXIDVER_TXMINORVER_MASK           0x000000FFu#define _EMAC_TXIDVER_TXMINORVER_SHIFT          0u#define  EMAC_TXIDVER_TXMINORVER_DEFAULT        0x00000000u/******************************************************************************\* _____________________* |                   |* |  TXCONTROL        |* |___________________|** TXCONTROL         - TX Control Register** FIELDS (msb -> lsb)* (rw)  TXEN        - Transmit Enable** MACROS SUPPORTED*  EMAC_FMK     y*  EMAC_FMKS    y*  EMAC_FMKCHF  .*  EMAC_ADDR    y*  EMAC_REG     y*  EMAC_RGET    y*  EMAC_RSET    y*  EMAC_FGET    y*  EMAC_FSET    y*  EMAC_FSETS   .*  EMAC_RGETI   .*  EMAC_RSETI   .*  EMAC_FGETI   .*  EMAC_FSETI   .*  EMAC_FSETSI  .