?? csl_emifahal.h
字號:
* SDEXT - SDRAM extension register** FIELDS (msb -> lsb)* (rw) WR2RD* (rw) WR2DEAC* (rw) WR2WR* (rw) R2WDQM* (rw) RD2WR* (rw) RD2DEAC* (rw) RD2RD* (rw) THZP* (rw) TWR* (rw) TRRD* (rw) TRAS* (rw) TCL*\******************************************************************************/ #define _EMIFA_SDEXT_OFFSET 8 #define _EMIFA_SDEXT_ADDR 0x01800020u #define _EMIFA_SDEXT_WR2RD_MASK 0x00100000u #define _EMIFA_SDEXT_WR2RD_SHIFT 0x00000014u #define EMIFA_SDEXT_WR2RD_DEFAULT 0x00000001u #define EMIFA_SDEXT_WR2RD_OF(x) _VALUEOF(x) #define _EMIFA_SDEXT_WR2DEAC_MASK 0x000C0000u #define _EMIFA_SDEXT_WR2DEAC_SHIFT 0x00000012u #define EMIFA_SDEXT_WR2DEAC_DEFAULT 0x00000001u #define EMIFA_SDEXT_WR2DEAC_OF(x) _VALUEOF(x) #define _EMIFA_SDEXT_WR2WR_MASK 0x00020000u #define _EMIFA_SDEXT_WR2WR_SHIFT 0x00000011u #define EMIFA_SDEXT_WR2WR_DEFAULT 0x00000001u #define EMIFA_SDEXT_WR2WR_OF(x) _VALUEOF(x) #define _EMIFA_SDEXT_R2WDQM_MASK 0x00018000u #define _EMIFA_SDEXT_R2WDQM_SHIFT 0x0000000Fu #define EMIFA_SDEXT_R2WDQM_DEFAULT 0x00000002u #define EMIFA_SDEXT_R2WDQM_OF(x) _VALUEOF(x) #define _EMIFA_SDEXT_RD2WR_MASK 0x00007000u #define _EMIFA_SDEXT_RD2WR_SHIFT 0x0000000Cu #define EMIFA_SDEXT_RD2WR_DEFAULT 0x00000005u #define EMIFA_SDEXT_RD2WR_OF(x) _VALUEOF(x) #define _EMIFA_SDEXT_RD2DEAC_MASK 0x00000C00u #define _EMIFA_SDEXT_RD2DEAC_SHIFT 0x0000000Au #define EMIFA_SDEXT_RD2DEAC_DEFAULT 0x00000003u #define EMIFA_SDEXT_RD2DEAC_OF(x) _VALUEOF(x) #define _EMIFA_SDEXT_RD2RD_MASK 0x00000200u #define _EMIFA_SDEXT_RD2RD_SHIFT 0x00000009u #define EMIFA_SDEXT_RD2RD_DEFAULT 0x00000001u #define EMIFA_SDEXT_RD2RD_OF(x) _VALUEOF(x) #define _EMIFA_SDEXT_THZP_MASK 0x00000180u #define _EMIFA_SDEXT_THZP_SHIFT 0x00000007u #define EMIFA_SDEXT_THZP_DEFAULT 0x00000002u #define EMIFA_SDEXT_THZP_OF(x) _VALUEOF(x) #define _EMIFA_SDEXT_TWR_MASK 0x00000060u #define _EMIFA_SDEXT_TWR_SHIFT 0x00000005u #define EMIFA_SDEXT_TWR_DEFAULT 0x00000001u #define EMIFA_SDEXT_TWR_OF(x) _VALUEOF(x) #define _EMIFA_SDEXT_TRRD_MASK 0x00000010u #define _EMIFA_SDEXT_TRRD_SHIFT 0x00000004u #define EMIFA_SDEXT_TRRD_DEFAULT 0x00000001u #define EMIFA_SDEXT_TRRD_OF(x) _VALUEOF(x) #define _EMIFA_SDEXT_TRAS_MASK 0x0000000Eu #define _EMIFA_SDEXT_TRAS_SHIFT 0x00000001u #define EMIFA_SDEXT_TRAS_DEFAULT 0x00000007u #define EMIFA_SDEXT_TRAS_OF(x) _VALUEOF(x) #define _EMIFA_SDEXT_TCL_MASK 0x00000001u #define _EMIFA_SDEXT_TCL_SHIFT 0x00000000u #define EMIFA_SDEXT_TCL_DEFAULT 0x00000001u #define EMIFA_SDEXT_TCL_OF(x) _VALUEOF(x) #define EMIFA_SDEXT_OF(x) _VALUEOF(x) #define EMIFA_SDEXT_DEFAULT (Uint32)( \ _PER_FDEFAULT(EMIFA,SDEXT,WR2RD)\ |_PER_FDEFAULT(EMIFA,SDEXT,WR2DEAC)\ |_PER_FDEFAULT(EMIFA,SDEXT,WR2WR)\ |_PER_FDEFAULT(EMIFA,SDEXT,R2WDQM)\ |_PER_FDEFAULT(EMIFA,SDEXT,RD2WR)\ |_PER_FDEFAULT(EMIFA,SDEXT,RD2DEAC)\ |_PER_FDEFAULT(EMIFA,SDEXT,RD2RD)\ |_PER_FDEFAULT(EMIFA,SDEXT,THZP)\ |_PER_FDEFAULT(EMIFA,SDEXT,TWR)\ |_PER_FDEFAULT(EMIFA,SDEXT,TRRD)\ |_PER_FDEFAULT(EMIFA,SDEXT,TRAS)\ |_PER_FDEFAULT(EMIFA,SDEXT,TCL)\ ) #define EMIFA_SDEXT_RMK(wr2rd,wr2deac,wr2wr,r2wdqm,rd2wr,rd2deac,\ rd2rd,thzp,twr,trrd,tras,tcl) (Uint32)( \ _PER_FMK(EMIFA,SDEXT,WR2RD,wr2rd)\ |_PER_FMK(EMIFA,SDEXT,WR2DEAC,wr2deac)\ |_PER_FMK(EMIFA,SDEXT,WR2WR,wr2wr)\ |_PER_FMK(EMIFA,SDEXT,R2WDQM,r2wdqm)\ |_PER_FMK(EMIFA,SDEXT,RD2WR,rd2wr)\ |_PER_FMK(EMIFA,SDEXT,RD2DEAC,rd2deac)\ |_PER_FMK(EMIFA,SDEXT,RD2RD,rd2rd)\ |_PER_FMK(EMIFA,SDEXT,THZP,thzp)\ |_PER_FMK(EMIFA,SDEXT,TWR,twr)\ |_PER_FMK(EMIFA,SDEXT,TRRD,trrd)\ |_PER_FMK(EMIFA,SDEXT,TRAS,tras)\ |_PER_FMK(EMIFA,SDEXT,TCL,tcl)\ ) #define _EMIFA_SDEXT_FGET(FIELD)\ _PER_FGET(_EMIFA_SDEXT_ADDR,EMIFA,SDEXT,##FIELD) #define _EMIFA_SDEXT_FSET(FIELD,field)\ _PER_FSET(_EMIFA_SDEXT_ADDR,EMIFA,SDEXT,##FIELD,field) #define _EMIFA_SDEXT_FSETS(FIELD,SYM)\ _PER_FSETS(_EMIFA_SDEXT_ADDR,EMIFA,SDEXT,##FIELD,##SYM)/******************************************************************************\* _____________________* | |* | C E x S E C |* |___________________|** CESEC0 - CE space secondary control register 0* CESEC1 - CE space secondary control register 1* CESEC2 - CE space secondary control register 2* CESEC3 - CE space secondary control register 3** FIELDS (msb -> lsb)* (rw) SNCCLK* (rw) RENEN* (rw) CEEXT* (rw) SYNCWL* (rw) SYNCRL*\******************************************************************************/ #define _EMIFA_CESEC0_OFFSET 18 #define _EMIFA_CESEC1_OFFSET 17 #define _EMIFA_CESEC2_OFFSET 20 #define _EMIFA_CESEC3_OFFSET 21 #define _EMIFA_CESEC0_ADDR 0x01800048u #define _EMIFA_CESEC1_ADDR 0x01800044u #define _EMIFA_CESEC2_ADDR 0x01800050u #define _EMIFA_CESEC3_ADDR 0x01800054u #define _EMIFA_CESEC_SNCCLK_MASK 0x00000040u #define _EMIFA_CESEC_SNCCLK_SHIFT 0x00000006u #define EMIFA_CESEC_SNCCLK_DEFAULT 0x00000000u #define EMIFA_CESEC_SNCCLK_OF(x) _VALUEOF(x) #define EMIFA_CESEC_SNCCLK_ECLKOUT1 0x00000000u #define EMIFA_CESEC_SNCCLK_ECLKOUT2 0x00000001u #define _EMIFA_CESEC_RENEN_MASK 0x00000020u #define _EMIFA_CESEC_RENEN_SHIFT 0x00000005u #define EMIFA_CESEC_RENEN_DEFAULT 0x00000000u #define EMIFA_CESEC_RENEN_OF(x) _VALUEOF(x) #define EMIFA_CESEC_RENEN_ADS 0x00000000u #define EMIFA_CESEC_RENEN_READ 0x00000001u #define _EMIFA_CESEC_CEEXT_MASK 0x00000010u #define _EMIFA_CESEC_CEEXT_SHIFT 0x00000004u #define EMIFA_CESEC_CEEXT_DEFAULT 0x00000000u #define EMIFA_CESEC_CEEXT_OF(x) _VALUEOF(x) #define EMIFA_CESEC_CEEXT_INACTIVE 0x00000000u #define EMIFA_CESEC_CEEXT_ACTIVE 0x00000001u #define _EMIFA_CESEC_SYNCWL_MASK 0x0000000Cu #define _EMIFA_CESEC_SYNCWL_SHIFT 0x00000002u #define EMIFA_CESEC_SYNCWL_DEFAULT 0x00000000u #define EMIFA_CESEC_SYNCWL_OF(x) _VALUEOF(x) #define EMIFA_CESEC_SYNCWL_0CYCLE 0x00000000u #define EMIFA_CESEC_SYNCWL_1CYCLE 0x00000001u #define EMIFA_CESEC_SYNCWL_2CYCLE 0x00000002u #define EMIFA_CESEC_SYNCWL_3CYCLE 0x00000003u #define _EMIFA_CESEC_SYNCRL_MASK 0x00000003u #define _EMIFA_CESEC_SYNCRL_SHIFT 0x00000000u #define EMIFA_CESEC_SYNCRL_DEFAULT 0x00000002u #define EMIFA_CESEC_SYNCRL_OF(x) _VALUEOF(x) #define EMIFA_CESEC_SYNCRL_0CYCLE 0x00000000u #define EMIFA_CESEC_SYNCRL_1CYCLE 0x00000001u #define EMIFA_CESEC_SYNCRL_2CYCLE 0x00000002u #define EMIFA_CESEC_SYNCRL_3CYCLE 0x00000003u #define EMIFA_CESEC_OF(x) _VALUEOF(x) #define EMIFA_CESEC_DEFAULT (Uint32)( \ _PER_FDEFAULT(EMIFA,CESEC,SNCCLK)\ |_PER_FDEFAULT(EMIFA,CESEC,RENEN)\ |_PER_FDEFAULT(EMIFA,CESEC,CEEXT)\ |_PER_FDEFAULT(EMIFA,CESEC,SYNCWL)\ |_PER_FDEFAULT(EMIFA,CESEC,SYNCRL)\ ) #define EMIFA_CESEC_RMK(sncclk,renen,ceext,syncwl,syncrl)\ (Uint32)( \ _PER_FMK(EMIFA,CESEC,SNCCLK,sncclk)\ |_PER_FMK(EMIFA,CESEC,RENEN,renen)\ |_PER_FMK(EMIFA,CESEC,CEEXT,ceext)\ |_PER_FMK(EMIFA,CESEC,SYNCWL,syncwl)\ |_PER_FMK(EMIFA,CESEC,SYNCRL,syncrl)\ ) #define _EMIFA_CESEC_FGET(N,FIELD)\ _PER_FGET(_EMIFA_CESEC##N##_ADDR,EMIFA,CESEC,##FIELD) #define _EMIFA_CESEC_FSET(N,FIELD,f)\ _PER_FSET(_EMIFA_CESEC##N##_ADDR,EMIFA,CESEC,##FIELD,f) #define _EMIFA_CESEC_FSETS(N,FIELD,SYM)\ _PER_FSETS(_EMIFA_CESEC##N##_ADDR,EMIFA,CESEC,##FIELD,##SYM) #define _EMIFA_CESEC0_FGET(FIELD) _EMIFA_CESEC_FGET(0,##FIELD) #define _EMIFA_CESEC1_FGET(FIELD) _EMIFA_CESEC_FGET(1,##FIELD) #define _EMIFA_CESEC2_FGET(FIELD) _EMIFA_CESEC_FGET(2,##FIELD) #define _EMIFA_CESEC3_FGET(FIELD) _EMIFA_CESEC_FGET(3,##FIELD) #define _EMIFA_CESEC0_FSET(FIELD,f) _EMIFA_CESEC_FSET(0,##FIELD,f) #define _EMIFA_CESEC1_FSET(FIELD,f) _EMIFA_CESEC_FSET(1,##FIELD,f) #define _EMIFA_CESEC2_FSET(FIELD,f) _EMIFA_CESEC_FSET(2,##FIELD,f) #define _EMIFA_CESEC3_FSET(FIELD,f) _EMIFA_CESEC_FSET(3,##FIELD,f) #define _EMIFA_CESEC0_FSETS(FIELD,SYM) _EMIFA_CESEC_FSETS(0,##FIELD,##SYM) #define _EMIFA_CESEC1_FSETS(FIELD,SYM) _EMIFA_CESEC_FSETS(1,##FIELD,##SYM) #define _EMIFA_CESEC2_FSETS(FIELD,SYM) _EMIFA_CESEC_FSETS(2,##FIELD,##SYM) #define _EMIFA_CESEC3_FSETS(FIELD,SYM) _EMIFA_CESEC_FSETS(3,##FIELD,##SYM) /******************************************************************************\* _____________________* | |* | P D T C T L |* |___________________|** PDTCTL - Peripheral device transfer (PDT) control** FIELDS (msb -> lsb)* (rw) PDTWL* (rw) PDTRL*\******************************************************************************/ #define _EMIFA_PDTCTL_OFFSET 16 #define _EMIFA_PDTCTL_ADDR 0x01800040u #define _EMIFA_PDTCTL_PDTWL_MASK 0x0000000Cu #define _EMIFA_PDTCTL_PDTWL_SHIFT 0x00000002u #define EMIFA_PDTCTL_PDTWL_DEFAULT 0x00000000u #define EMIFA_PDTCTL_PDTWL_OF(x) _VALUEOF(x) #define EMIFA_PDTCTL_PDTWL_0CYCLE 0x00000000u #define EMIFA_PDTCTL_PDTWL_1CYCLE 0x00000001u #define EMIFA_PDTCTL_PDTWL_2CYCLE 0x00000002u #define EMIFA_PDTCTL_PDTWL_3CYCLE 0x00000003u #define _EMIFA_PDTCTL_PDTRL_MASK 0x000C0003u #define _EMIFA_PDTCTL_PDTRL_SHIFT 0x00000000u #define EMIFA_PDTCTL_PDTRL_DEFAULT 0x00000000u #define EMIFA_PDTCTL_PDTRL_OF(x) _VALUEOF(x) #define EMIFA_PDTCTL_PDTRL_0CYCLE 0x00000000u #define EMIFA_PDTCTL_PDTRL_1CYCLE 0x00000001u #define EMIFA_PDTCTL_PDTRL_2CYCLE 0x00000002u #define EMIFA_PDTCTL_PDTRL_3CYCLE 0x00000003u #define EMIFA_PDTCTL_DEFAULT (Uint32)( \ _PER_FDEFAULT(EMIFA,PDTCTL,PDTWL)\ |_PER_FDEFAULT(EMIFA,PDTCTL,PDTRL)\ ) #define EMIFA_PDTCTL_RMK(pdtwl,pdtrl) (Uint32)( \ _PER_FMK(EMIFA,PDTCTL,PDTWL,pdtwl)\ |_PER_FMK(EMIFA,PDTCTL,PDTRL,pdtrl)\ ) #define _EMIFA_PDTCTL_FGET(FIELD)\ _PER_FGET(_EMIFA_PDTCTL_ADDR,EMIFA,PDTCTL,##FIELD) #define _EMIFA_PDTCTL_FSET(FIELD,field)\ _PER_FSET(_EMIFA_PDTCTL_ADDR,EMIFA,PDTCTL,##FIELD,field) #define _EMIFA_PDTCTL_FSETS(FIELD,SYM)\ _PER_FSETS(_EMIFA_PDTCTL_ADDR,EMIFA,PDTCTL,##FIELD,##SYM)#endif /* EMIFA_SUPPORT */#endif /* _CSL_EMIFHAL_H_ *//******************************************************************************\* End of csl_emifahal.h\******************************************************************************/?? 快捷鍵說明
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