AREA	|C$$code|, CODE, READONLY

		GET		Option.inc

; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F ; available on ARM Arch 4 and later

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled


; --- Amount of memory (in bytes) allocated for stacks

Len_FIQ_Stack    EQU     256
Len_IRQ_Stack    EQU     256
Len_ABT_Stack    EQU     256
Len_UND_Stack    EQU     256
Len_SVC_Stack    EQU     1024

; Offsets will be loaded as immediate values.
; Offsets must be 8 byte aligned.

Offset_FIQ_Stack         EQU     0
Offset_IRQ_Stack         EQU     Offset_FIQ_Stack + Len_FIQ_Stack
Offset_ABT_Stack         EQU     Offset_IRQ_Stack + Len_IRQ_Stack
Offset_UND_Stack         EQU     Offset_ABT_Stack + Len_ABT_Stack
Offset_SVC_Stack         EQU     Offset_UND_Stack + Len_UND_Stack



		EXPORT	__user_initial_stackheap

__user_initial_stackheap

		LDR     r0, =top_of_stacks

		MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
		SUB     sp, r0, #Offset_FIQ_Stack

		MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
		SUB     sp, r0, #Offset_IRQ_Stack

		MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
		SUB     sp, r0, #Offset_ABT_Stack

		MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit ; No interrupts
		SUB     sp, r0, #Offset_UND_Stack

		MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
		SUB     r1, r0, #Offset_SVC_Stack

		IMPORT  |Image$$ZI$$Limit|
		LDR		r0, =|Image$$ZI$$Limit|
		
		MOV		pc,lr


		LTORG
   
		END