?? upsd3400.h
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/*--------------------------------------------------------------------------
upsd3400.h
Version:
September 13, 2005 Ver 1.1 - Updated disclaimer.
February 18, 2005 Version 2.1 - Corrected PSD VM and UART1 register
definitions.
September 9, 2004 Version 2.0 - Initial Version.
Dependencies: None.
Description:
Header file for uPSD3400 microcontroller.
Compilers:
Raisonance, Keil
Copyright (c) 2005 STMicroelectronics
THIS INFORMATION (or THIS SOFTWARE or THIS DOCUMENT) IS FOR GUIDANCE ONLY. ST
MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
SOFTWARE nor for any infringement of patents or other rights of third parties
which may result from its use. ST MICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
ANY DIRECT, INDIRECT INCIDENTAL OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
CLAIMS ARISING IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE,
OR USE OF THIS SOFTWARE. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all
information previously supplied. STMicroelectronics products are not authorized
for use as critical components in life support devices or systems without the
express written approval of STMicroelectronics.
--------------------------------------------------------------------------*/
// Check for previous defines
#ifndef _uPSD3400h_
#define _uPSD3400h_
//-- Data Type Definitions ---------------------------------------------------
//Specify the SFR and bit definition macros for the specific compiler used.
#ifdef __RC51__ //Compiler: Raisonance
#define DEFINE_SFR(REG,ADR) \
at ADR sfr REG;
#define DEFINE_SFR_BIT(SFR_BIT,ADR) \
at ADR sbit SFR_BIT;
#else
#ifdef __C51__ //Compiler: Keil
#define DEFINE_SFR(REG,ADR) \
sfr REG = ADR;
#define DEFINE_SFR_BIT(SFR_BIT,ADR) \
sbit SFR_BIT = ADR;
#else //Compiler: Other
// User would need to add definitions for other compilers here...
#endif
#endif
typedef struct // general structure of 8 bit register allowing bit access
{
unsigned char bit0 : 1;
unsigned char bit1 : 1;
unsigned char bit2 : 1;
unsigned char bit3 : 1;
unsigned char bit4 : 1;
unsigned char bit5 : 1;
unsigned char bit6 : 1;
unsigned char bit7 : 1;
} Register;
typedef union // allow bit or byte access to registers
{
char byte;
Register bits;
} Mix_Reg;
typedef union // allow bit or byte access to registers
{
char byte;
Register bits;
} SFR_Reg;
/* ------------------------------ */
/* Standard PSD Registers */
/* ------------------------------ */
typedef struct REG_PSD_struct {
unsigned char DATAIN_A; // PSD_REG_BASE +0x00
unsigned char DATAIN_B; // +0x01
unsigned char CONTROL_A; // +0x02
unsigned char CONTROL_B; // +0x03
unsigned char DATAOUT_A; // +0x04
unsigned char DATAOUT_B; // +0x05
unsigned char DIRECTION_A; // +0x06
unsigned char DIRECTION_B; // +0x07
unsigned char DRIVE_A; // +0x08
unsigned char DRIVE_B; // +0x09
unsigned char IMC_A; // +0x0A
unsigned char IMC_B; // +0x0B
unsigned char OUTENABLE_A; // +0x0C
unsigned char OUTENABLE_B; // +0x0D
unsigned char res2[2]; // spacer
unsigned char DATAIN_C; // +0x10
unsigned char DATAIN_D; // +0x11
unsigned char DATAOUT_C; // +0x12
unsigned char DATAOUT_D; // +0x13
unsigned char DIRECTION_C; // +0x14
unsigned char DIRECTION_D; // +0x15
unsigned char DRIVE_C; // +0x16
unsigned char DRIVE_D; // +0x17
unsigned char IMC_C; // +0x18
unsigned char res1a; // spacer
unsigned char OUTENABLE_C; // +0x1A
unsigned char OUTENABLE_D; // +0x1B
unsigned char res4[4]; // spacer
unsigned char OMC_AB; // +0x20
unsigned char OMC_BC; // +0x21
unsigned char OMCMASK_AB; // +0x22
unsigned char OMCMASK_BC; // +0x23
unsigned char res8c[0x8C]; // spacer
unsigned char PMMR0; // +0xB0
unsigned char res1[3]; // spacer
unsigned char PMMR2; // +0xB4
unsigned char res0B[0x0B]; // spacer
unsigned char MAINPROTECT; // +0xC0
unsigned char res1b; // spacer
unsigned char ALTPROTECT; // +0xC2
unsigned char res4a[4]; // spacer
unsigned char PMMR3; // +0xC7
unsigned char res18[0x18]; // spacer
unsigned char PAGE; // +0xE0
unsigned char res1c; // spacer
unsigned char VM; // +0xE2
unsigned char res29[0x1d]; // spacer
} PSD_REGS;
//****************** PSD control register bit definitions *********
//PSD PORTA
#define PA0 bit0
#define PA1 bit1
#define PA2 bit2
#define PA3 bit3
#define PA4 bit4
#define PA5 bit5
#define PA6 bit6
#define PA7 bit7
//PSD PORTB
#define PB0 bit0
#define PB1 bit1
#define PB2 bit2
#define PB3 bit3
#define PB4 bit4
#define PB5 bit5
#define PB6 bit6
#define PB7 bit7
//PSD PORTC
#define PC0 bit0
#define PC1 bit1
#define PC2 bit2
#define PC3 bit3
#define PC4 bit4
#define PC5 bit5
#define PC6 bit6
#define PC7 bit7
//PSD PORTD
#define PD1 bit1
#define PD2 bit2
//PSD PMMR0
#define APD_ENABLE bit1
#define PLD_TURBO bit3
#define PLD_ARRAY_CLK bit4
#define PLD_MCELL_CLK bit5
//PSD PMMR2
#define PLD_CNTL0 bit2
#define PLD_CNTL1 bit3
#define PLD_CNTL2 bit4
#define PLD_ALE bit5
#define PLD_DBE bit6
//PSD PMMR3
#define FORCE_PD bit1
//PSD VM
#define SFL_CODE bit1
#define MFL_CODE bit2
#define SFL_DATA bit3
#define MFL_DATA bit4
#define PIO_EN bit7
// Common Misc. Defines...
#ifndef TRUE
#define TRUE 0x01
#endif
#ifndef FALSE
#define FALSE 0x00
#endif
#ifndef ON
#define ON 0x01
#endif
#ifndef OFF
#define OFF 0x00
#endif
#ifndef NULL
#define NULL 0x00
#endif
/* ------------------------------ */
/* Standard 8051 MCU Registers */
/* ------------------------------ */
//DEFINE_SFR(P0,0x80) // Port 0 - Always used for External Memory Access (no access)
DEFINE_SFR(P1,0x90) // Port 1
//DEFINE_SFR(P2,0xA0) // Port 2 - Always used for External Memory Access (no access)
DEFINE_SFR(P3,0xB0) // Port 3
DEFINE_SFR(PSW,0xD0) // Program Status Word
DEFINE_SFR(ACC,0xE0) // Accumulator
DEFINE_SFR(B,0xF0) // Register B
DEFINE_SFR(SP,0x81) // Stack Pointer
DEFINE_SFR(DPL,0x82) // Data Pointer low byte
DEFINE_SFR(DPH,0x83) // Data Pointer high byte
DEFINE_SFR(PCON,0x87) // MCU Power Control Register
DEFINE_SFR(TCON,0x88) // Timer / Counter Control
DEFINE_SFR(TMOD,0x89) // Timer / Counter Mode
DEFINE_SFR(TL0,0x8A) // Timer 0 low byte
DEFINE_SFR(TL1,0x8B) // Timer 1 low byte
DEFINE_SFR(TH0,0x8C) // Timer 0 high byte
DEFINE_SFR(TH1,0x8D) // Timer 1 high byte
DEFINE_SFR(IE,0xA8) // Interrupt Enable (main)
DEFINE_SFR(IP,0xB8) // Interrupt Priority (main)
DEFINE_SFR(SCON,0x98) // UART0 Serial Control
DEFINE_SFR(SCON0,0x98) // SCON also known as SCON0
DEFINE_SFR(SBUF,0x99) // UART0 Serial Buffer
DEFINE_SFR(SBUF0,0x99) // SBUF also known as SBUF0
/* ------------------------ */
/* Common 8052 Extensions */
/* ------------------------ */
DEFINE_SFR(T2CON,0xC8) // Timer 2 Control
DEFINE_SFR(RCAP2L,0xCA) // Timer 2 Reload low byte
DEFINE_SFR(RCAP2H,0xCB) // Timer 2 Reload high byte
DEFINE_SFR(TL2,0xCC) // Timer 2 low byte
DEFINE_SFR(TH2,0xCD) // Timer 2 high byte
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