?? at91rm9200.inc
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SSC_TNCR # 4 ;- Transmit Next Counter Register
SSC_PTCR # 4 ;- PDC Transfer Control Register
SSC_PTSR # 4 ;- PDC Transfer Status Register
;- -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
AT91C_SSC_RXEN EQU (0x1:SHL:0) ;- (SSC) Receive Enable
AT91C_SSC_RXDIS EQU (0x1:SHL:1) ;- (SSC) Receive Disable
AT91C_SSC_TXEN EQU (0x1:SHL:8) ;- (SSC) Transmit Enable
AT91C_SSC_TXDIS EQU (0x1:SHL:9) ;- (SSC) Transmit Disable
AT91C_SSC_SWRST EQU (0x1:SHL:15) ;- (SSC) Software Reset
;- -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
AT91C_SSC_CKS EQU (0x3:SHL:0) ;- (SSC) Receive/Transmit Clock Selection
AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock
AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal
AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin
AT91C_SSC_CKO EQU (0x7:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
AT91C_SSC_CKO_NONE EQU (0x0:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
AT91C_SSC_CKO_CONTINOUS EQU (0x1:SHL:2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
AT91C_SSC_CKO_DATA_TX EQU (0x2:SHL:2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
AT91C_SSC_CKI EQU (0x1:SHL:5) ;- (SSC) Receive/Transmit Clock Inversion
AT91C_SSC_CKG EQU (0x3:SHL:6) ;- (SSC) Receive/Transmit Clock Gating Selection
AT91C_SSC_CKG_NONE EQU (0x0:SHL:6) ;- (SSC) Receive/Transmit Clock Gating: None, continuous clock
AT91C_SSC_CKG_LOW EQU (0x1:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF Low
AT91C_SSC_CKG_HIGH EQU (0x2:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF High
AT91C_SSC_START EQU (0xF:SHL:8) ;- (SSC) Receive/Transmit Start Selection
AT91C_SSC_START_CONTINOUS EQU (0x0:SHL:8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
AT91C_SSC_START_TX EQU (0x1:SHL:8) ;- (SSC) Transmit/Receive start
AT91C_SSC_START_LOW_RF EQU (0x2:SHL:8) ;- (SSC) Detection of a low level on RF input
AT91C_SSC_START_HIGH_RF EQU (0x3:SHL:8) ;- (SSC) Detection of a high level on RF input
AT91C_SSC_START_FALL_RF EQU (0x4:SHL:8) ;- (SSC) Detection of a falling edge on RF input
AT91C_SSC_START_RISE_RF EQU (0x5:SHL:8) ;- (SSC) Detection of a rising edge on RF input
AT91C_SSC_START_LEVEL_RF EQU (0x6:SHL:8) ;- (SSC) Detection of any level change on RF input
AT91C_SSC_START_EDGE_RF EQU (0x7:SHL:8) ;- (SSC) Detection of any edge on RF input
AT91C_SSC_START_0 EQU (0x8:SHL:8) ;- (SSC) Compare 0
AT91C_SSC_STOP EQU (0x1:SHL:12) ;- (SSC) Receive Stop Selection
AT91C_SSC_STTOUT EQU (0x1:SHL:15) ;- (SSC) Receive/Transmit Start Output Selection
AT91C_SSC_STTDLY EQU (0xFF:SHL:16) ;- (SSC) Receive/Transmit Start Delay
AT91C_SSC_PERIOD EQU (0xFF:SHL:24) ;- (SSC) Receive/Transmit Period Divider Selection
;- -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
AT91C_SSC_DATLEN EQU (0x1F:SHL:0) ;- (SSC) Data Length
AT91C_SSC_LOOP EQU (0x1:SHL:5) ;- (SSC) Loop Mode
AT91C_SSC_MSBF EQU (0x1:SHL:7) ;- (SSC) Most Significant Bit First
AT91C_SSC_DATNB EQU (0xF:SHL:8) ;- (SSC) Data Number per Frame
AT91C_SSC_FSLEN EQU (0xF:SHL:16) ;- (SSC) Receive/Transmit Frame Sync length
AT91C_SSC_FSOS EQU (0x7:SHL:20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
AT91C_SSC_FSOS_NONE EQU (0x0:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
AT91C_SSC_FSOS_NEGATIVE EQU (0x1:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
AT91C_SSC_FSOS_POSITIVE EQU (0x2:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
AT91C_SSC_FSOS_LOW EQU (0x3:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
AT91C_SSC_FSOS_HIGH EQU (0x4:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
AT91C_SSC_FSOS_TOGGLE EQU (0x5:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
AT91C_SSC_FSEDGE EQU (0x1:SHL:24) ;- (SSC) Frame Sync Edge Detection
;- -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
;- -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
AT91C_SSC_DATDEF EQU (0x1:SHL:5) ;- (SSC) Data Default Value
AT91C_SSC_FSDEN EQU (0x1:SHL:23) ;- (SSC) Frame Sync Data Enable
;- -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
AT91C_SSC_TXRDY EQU (0x1:SHL:0) ;- (SSC) Transmit Ready
AT91C_SSC_TXEMPTY EQU (0x1:SHL:1) ;- (SSC) Transmit Empty
AT91C_SSC_ENDTX EQU (0x1:SHL:2) ;- (SSC) End Of Transmission
AT91C_SSC_TXBUFE EQU (0x1:SHL:3) ;- (SSC) Transmit Buffer Empty
AT91C_SSC_RXRDY EQU (0x1:SHL:4) ;- (SSC) Receive Ready
AT91C_SSC_OVRUN EQU (0x1:SHL:5) ;- (SSC) Receive Overrun
AT91C_SSC_ENDRX EQU (0x1:SHL:6) ;- (SSC) End of Reception
AT91C_SSC_RXBUFF EQU (0x1:SHL:7) ;- (SSC) Receive Buffer Full
AT91C_SSC_CP0 EQU (0x1:SHL:8) ;- (SSC) Compare 0
AT91C_SSC_CP1 EQU (0x1:SHL:9) ;- (SSC) Compare 1
AT91C_SSC_TXSYN EQU (0x1:SHL:10) ;- (SSC) Transmit Sync
AT91C_SSC_RXSYN EQU (0x1:SHL:11) ;- (SSC) Receive Sync
AT91C_SSC_TXENA EQU (0x1:SHL:16) ;- (SSC) Transmit Enable
AT91C_SSC_RXENA EQU (0x1:SHL:17) ;- (SSC) Receive Enable
;- -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
;- -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
;- -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Usart
;- *****************************************************************************
^ 0 ;- AT91S_USART
US_CR # 4 ;- Control Register
US_MR # 4 ;- Mode Register
US_IER # 4 ;- Interrupt Enable Register
US_IDR # 4 ;- Interrupt Disable Register
US_IMR # 4 ;- Interrupt Mask Register
US_CSR # 4 ;- Channel Status Register
US_RHR # 4 ;- Receiver Holding Register
US_THR # 4 ;- Transmitter Holding Register
US_BRGR # 4 ;- Baud Rate Generator Register
US_RTOR # 4 ;- Receiver Time-out Register
US_TTGR # 4 ;- Transmitter Time-guard Register
# 20 ;- Reserved
US_FIDI # 4 ;- FI_DI_Ratio Register
US_NER # 4 ;- Nb Errors Register
US_XXR # 4 ;- XON_XOFF Register
US_IF # 4 ;- IRDA_FILTER Register
# 176 ;- Reserved
US_RPR # 4 ;- Receive Pointer Register
US_RCR # 4 ;- Receive Counter Register
US_TPR # 4 ;- Transmit Pointer Register
US_TCR # 4 ;- Transmit Counter Register
US_RNPR # 4 ;- Receive Next Pointer Register
US_RNCR # 4 ;- Receive Next Counter Register
US_TNPR # 4 ;- Transmit Next Pointer Register
US_TNCR # 4 ;- Transmit Next Counter Register
US_PTCR # 4 ;- PDC Transfer Control Register
US_PTSR # 4 ;- PDC Transfer Status Register
;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
AT91C_US_RSTSTA EQU (0x1:SHL:8) ;- (USART) Reset Status Bits
AT91C_US_STTBRK EQU (0x1:SHL:9) ;- (USART) Start Break
AT91C_US_STPBRK EQU (0x1:SHL:10) ;- (USART) Stop Break
AT91C_US_STTTO EQU (0x1:SHL:11) ;- (USART) Start Time-out
AT91C_US_SENDA EQU (0x1:SHL:12) ;- (USART) Send Address
AT91C_US_RSTIT EQU (0x1:SHL:13) ;- (USART) Reset Iterations
AT91C_US_RSTNACK EQU (0x1:SHL:14) ;- (USART) Reset Non Acknowledge
AT91C_US_RETTO EQU (0x1:SHL:15) ;- (USART) Rearm Time-out
AT91C_US_DTREN EQU (0x1:SHL:16) ;- (USART) Data Terminal ready Enable
AT91C_US_DTRDIS EQU (0x1:SHL:17) ;- (USART) Data Terminal ready Disable
AT91C_US_RTSEN EQU (0x1:SHL:18) ;- (USART) Request to Send enable
AT91C_US_RTSDIS EQU (0x1:SHL:19) ;- (USART) Request to Send Disable
;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
AT91C_US_USMODE EQU (0xF:SHL:0) ;- (USART) Usart mode
AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal
AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485
AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking
AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem
AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA
AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking
AT91C_US_CLKS EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
AT91C_US_CLKS_CLOCK EQU (0x0:SHL:4) ;- (USART) Clock
AT91C_US_CLKS_FDIV1 EQU (0x1:SHL:4) ;- (USART) fdiv1
AT91C_US_CLKS_SLOW EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM)
AT91C_US_CLKS_EXT EQU (0x3:SHL:4) ;- (USART) External (SCK)
AT91C_US_CHRL EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
AT91C_US_CHRL_5_BITS EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits
AT91C_US_CHRL_6_BITS EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits
AT91C_US_CHRL_7_BITS EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits
AT91C_US_CHRL_8_BITS EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits
AT91C_US_SYNC EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select
AT91C_US_NBSTOP EQU (0x3:SHL:12) ;- (USART) Number of Stop bits
AT91C_US_NBSTOP_1_BIT EQU (0x0:SHL:12) ;- (USART) 1 stop bit
AT91C_US_NBSTOP_15_BIT EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
AT91C_US_NBSTOP_2_BIT EQU (0x2:SHL:12) ;- (USART) 2 stop bits
AT91C_US_MSBF EQU (0x1:SHL:16) ;- (USART) Bit Order
AT91C_US_MODE9 EQU (0x1:SHL:17) ;- (USART) 9-bit Character length
AT91C_US_CKLO EQU (0x1:SHL:18) ;- (USART) Clock Output Select
AT91C_US_OVER EQU (0x1:SHL:19) ;- (USART) Over Sampling Mode
AT91C_US_INACK EQU (0x1:SHL:20) ;- (USART) Inhibit Non Acknowledge
AT91C_US_DSNACK EQU (0x1:SHL:21) ;- (USART) Disable Successive NACK
AT91C_US_MAX_ITER EQU (0x1:SHL:24) ;- (USART) Number of Repetitions
AT91C_US_FILTER EQU (0x1:SHL:28) ;- (USART) Receive Line Filter
;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
AT91C_US_RXBRK EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break
AT91C_US_TIMEOUT EQU (0x1:SHL:8) ;- (USART) Receiver Time-out
AT91C_US_ITERATION EQU (0x1:SHL:10) ;- (USART) Max number of Repetitions Reached
AT91C_US_NACK EQU (0x1:SHL:13) ;- (USART) Non Acknowledge
AT91C_US_RIIC EQU (0x1:SHL:16) ;- (USART) Ring INdicator Input Change Flag
AT91C_US_DSRIC EQU (0x1:SHL:17) ;- (USART) Data Set Ready Input Change Flag
AT91C_US_DCDIC EQU (0x1:SHL:18) ;- (USART) Data Carrier Flag
AT91C_US_CTSIC EQU (0x1:SHL:19) ;- (USART) Clear To Send Input Change Flag
;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
AT91C_US_RI EQU (0x1:SHL:20) ;- (USART) Image of RI Input
AT91C_US_DSR EQU (0x1:SHL:21) ;- (USART) Image of DSR Input
AT91C_US_DCD EQU (0x1:SHL:22) ;- (USART) Image of DCD Input
AT91C_US_CTS EQU (0x1:SHL:23) ;- (USART) Image of CTS Input
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Two-wire Interface
;- *****************************************************************************
^ 0 ;- AT91S_TWI
TWI_CR # 4 ;- Control Register
TWI_MMR # 4 ;- Master Mode Register
TWI_SMR # 4 ;- Slave Mode Register
TWI_IADR # 4 ;- Internal Address Register
TWI_CWGR # 4 ;- Clock Waveform Generator Register
# 12 ;- Reserved
TWI_SR # 4 ;- Status Register
TWI_IER # 4 ;- Interrupt Enable Register
TWI_IDR # 4 ;- Interrupt Disable Register
TWI_IMR # 4 ;- Interrupt Mask Register
TWI_RHR # 4 ;- Receive Holding Register
TWI_THR # 4 ;- Transmit Holding Register
;- -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
AT91C_TWI_START EQU (0x1:SHL:0) ;- (TWI) Send a START Condition
AT91C_TWI_STOP EQU (0x1:SHL:1) ;- (TWI) Send a STOP Condition
AT91C_TWI_MSEN EQU (0x1:SHL:2) ;- (TWI) TWI Master Transfer Enabled
AT91C_TWI_MSDIS EQU (0x1:SHL:3) ;- (TWI) TWI Master Transfer Disabled
AT91C_TWI_SVEN EQU (0x1:SHL:4) ;- (TWI) TWI Slave Transfer Enabled
AT91C_TWI_SVDIS EQU (0x1:SHL:5) ;- (TWI) TWI Slave Transfer Disabled
AT91C_TWI_SWRST EQU (0x1:SHL:7) ;- (TWI) Software Reset
;- -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
AT91C_TWI_IADRSZ EQU (0x3:SHL:8) ;- (TWI) Internal Device Address Size
AT91C_TWI_IADRSZ_NO EQU (0x0:SHL:8) ;- (TWI) No internal device address
AT91C_TWI_IADRSZ_1_BYTE EQU (0x1:SHL:8) ;- (TWI) One-byte internal device address
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