/* * Used and modified for FripTV project 2007 * * Copyright (C) 2001-2004 the xine project * * This file is part of xine, a free video player. * * xine is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * xine is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA * * These are the MMX/MMX2/SSE optimized versions of memcpy * * This code was adapted from Linux Kernel sources by Nick Kurshev to * the mplayer program. (http://mplayer.sourceforge.net) * * Miguel Freitas split the #ifdefs into several specialized functions that * are benchmarked at runtime by xine. Some original comments from Nick * have been preserved documenting some MMX/SSE oddities. * Also added kernel memcpy function that seems faster than libc one. * *//* $Id$ */#ifndef MEMCPY_H#define MEMCPY_H/* Original comments from mplayer (file: aclib.c) This part of code was taken by me from Linux-2.4.3 and slightly modifiedfor MMX, MMX2, SSE instruction set. I have done it since linux uses page alignedblocks but mplayer uses weakly ordered data and original sources can notspeedup them. Only using PREFETCHNTA and MOVNTQ together have effect!>From IA-32 Intel Architecture Software Developer's Manual Volume 1,Order Number 245470:"10.4.6. Cacheability Control, Prefetch, and Memory Ordering Instructions"Data referenced by a program can be temporal (data will be used again) ornon-temporal (data will be referenced once and not reused in the immediatefuture). To make efficient use of the processor's caches, it is generallydesirable to cache temporal data and not cache non-temporal data. Overloadingthe processor's caches with non-temporal data is sometimes referred to as"polluting the caches".The non-temporal data is written to memory with Write-Combining semantics.The PREFETCHh instructions permits a program to load data into the processorat a suggested cache level, so that it is closer to the processors load andstore unit when it is needed. If the data is already present in a level ofthe cache hierarchy that is closer to the processor, the PREFETCHh instructionwill not result in any data movement.But we should you PREFETCHNTA: Non-temporal data fetch data into locationclose to the processor, minimizing cache pollution.The MOVNTQ (store quadword using non-temporal hint) instruction storespacked integer data from an MMX register to memory, using a non-temporal hint.The MOVNTPS (store packed single-precision floating-point values usingnon-temporal hint) instruction stores packed floating-point data from anXMM register to memory, using a non-temporal hint.The SFENCE (Store Fence) instruction controls write ordering by creating afence for memory store operations. This instruction guarantees that the resultsof every store instruction that precedes the store fence in program order isglobally visible before any store instruction that follows the fence. TheSFENCE instruction provides an efficient way of ensuring ordering betweenprocedures that produce weakly-ordered data and procedures that consume thatdata.If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru.*//*  mmx v.1 Note: Since we added alignment of destinition it speedups    of memory copying on PentMMX, Celeron-1 and P2 upto 12% versus    standard (non MMX-optimized) version.    Note: on K6-2+ it speedups memory copying upto 25% and          on K7 and P3 about 500% (5 times).*//* Additional notes on gcc assembly and processors: [MF]prefetch is specific for AMD processors, the intel ones should beprefetch0, prefetch1, prefetch2 which are not recognized by my gcc.prefetchnta is supported both on athlon and pentium 3.therefore i will take off prefetchnta instructions from the mmx1 versionto avoid problems on pentium mmx and k6-2.quote of the day:"Using prefetches efficiently is more of an art than a science"*/#if (C_HOSTCPU == X86) || (C_HOSTCPU == X86_64)#ifndef _MSC_VER/* linux kernel __memcpy (from: /include/asm/string.h) */static __inline__ void * linux_kernel_memcpy_impl (void * to, const void * from, size_t n){int d0, d1, d2;  if( n < 4 ) {    small_memcpy(to,from,n);  }  else    __asm__ __volatile__(    "rep ; movsl\n\t"    "testb $2,%b4\n\t"    "je 1f\n\t"    "movsw\n"    "1:\ttestb $1,%b4\n\t"    "je 2f\n\t"    "movsb\n"    "2:"    : "=&c" (d0), "=&D" (d1), "=&S" (d2)    :"0" (n/4), "q" (n),"1" ((long) to),"2" ((long) from)    : "memory");  return (to);}#define SSE_MMREG_SIZE 16#define MMX_MMREG_SIZE 8#define MMX1_MIN_LEN 0x800  /* 2K blocks */#define MIN_LEN 0x40  /* 64-byte blocks *//* SSE note: i tried to move 128 bytes a time instead of 64 but itdidn't make any measureable difference. i'm using 64 for the sake ofsimplicity. [MF] */static __inline__ void * sse_memcpy(void * to, const void * from, size_t len){  void *retval;  size_t i;  retval = to;  /* PREFETCH has effect even for MOVSB instruction ;) */  __asm__ __volatile__ (    "   prefetchnta (%0)\n"    "   prefetchnta 32(%0)\n"    "   prefetchnta 64(%0)\n"    "   prefetchnta 96(%0)\n"    "   prefetchnta 128(%0)\n"    "   prefetchnta 160(%0)\n"    "   prefetchnta 192(%0)\n"    "   prefetchnta 224(%0)\n"    "   prefetchnta 256(%0)\n"    "   prefetchnta 288(%0)\n"    : : "r" (from) );  if(len >= MIN_LEN)  {    register unsigned long int delta;    /* Align destinition to MMREG_SIZE -boundary */    delta = ((unsigned long int)to)&(SSE_MMREG_SIZE-1);    if(delta)    {      delta=SSE_MMREG_SIZE-delta;      len -= delta;      small_memcpy(to, from, delta);    }    i = len >> 6; /* len/64 */    len&=63;    if(((unsigned long)from) & 15)      /* if SRC is misaligned */      for(; i>0; i--)      {        __asm__ __volatile__ (        "prefetchnta 320(%0)\n"        "prefetchnta 352(%0)\n"        "movups (%0), %%xmm0\n"        "movups 16(%0), %%xmm1\n"        "movups 32(%0), %%xmm2\n"        "movups 48(%0), %%xmm3\n"        "movntps %%xmm0, (%1)\n"        "movntps %%xmm1, 16(%1)\n"        "movntps %%xmm2, 32(%1)\n"        "movntps %%xmm3, 48(%1)\n"        :: "r" (from), "r" (to) : "memory");        from = ((const unsigned char *)from) + 64;        to = ((unsigned char *)to) + 64;      }    else      /*         Only if SRC is aligned on 16-byte boundary.         It allows to use movaps instead of movups, which required data         to be aligned or a general-protection exception (#GP) is generated.      */      for(; i>0; i--)      {        __asm__ __volatile__ (        "prefetchnta 320(%0)\n"        "prefetchnta 352(%0)\n"        "movaps (%0), %%xmm0\n"        "movaps 16(%0), %%xmm1\n"        "movaps 32(%0), %%xmm2\n"        "movaps 48(%0), %%xmm3\n"        "movntps %%xmm0, (%1)\n"        "movntps %%xmm1, 16(%1)\n"        "movntps %%xmm2, 32(%1)\n"        "movntps %%xmm3, 48(%1)\n"        :: "r" (from), "r" (to) : "memory");        from = ((const unsigned char *)from) + 64;        to = ((unsigned char *)to) + 64;      }    /* since movntq is weakly-ordered, a "sfence"     * is needed to become ordered again. */    __asm__ __volatile__ ("sfence":::"memory");    /* enables to use FPU */    __asm__ __volatile__ ("emms":::"memory");  }  /*   *	Now do the tail of the block   */  if(len) linux_kernel_memcpy_impl(to, from, len);  return retval;}static __inline__ void * mmx_memcpy(void * to, const void * from, size_t len){  void *retval;  size_t i;  retval = to;  if(len >= MMX1_MIN_LEN)  {    register unsigned long int delta;    /* Align destinition to MMREG_SIZE -boundary */    delta = ((unsigned long int)to)&(MMX_MMREG_SIZE-1);    if(delta)    {      delta=MMX_MMREG_SIZE-delta;      len -= delta;      small_memcpy(to, from, delta);    }    i = len >> 6; /* len/64 */    len&=63;    for(; i>0; i--)    {      __asm__ __volatile__ (      "movq (%0), %%mm0\n"      "movq 8(%0), %%mm1\n"      "movq 16(%0), %%mm2\n"      "movq 24(%0), %%mm3\n"      "movq 32(%0), %%mm4\n"      "movq 40(%0), %%mm5\n"      "movq 48(%0), %%mm6\n"      "movq 56(%0), %%mm7\n"      "movq %%mm0, (%1)\n"      "movq %%mm1, 8(%1)\n"      "movq %%mm2, 16(%1)\n"      "movq %%mm3, 24(%1)\n"      "movq %%mm4, 32(%1)\n"      "movq %%mm5, 40(%1)\n"      "movq %%mm6, 48(%1)\n"      "movq %%mm7, 56(%1)\n"      :: "r" (from), "r" (to) : "memory");      from = ((const unsigned char *)from) + 64;      to = ((unsigned char *)to) + 64;    }    __asm__ __volatile__ ("emms":::"memory");  }  /*   *	Now do the tail of the block   */  if(len) linux_kernel_memcpy_impl(to, from, len);  return retval;}static __inline__ void * mmx2_memcpy(void * to, const void * from, size_t len){  void *retval;  size_t i;  retval = to;  /* PREFETCH has effect even for MOVSB instruction ;) */  __asm__ __volatile__ (    "   prefetchnta (%0)\n"    "   prefetchnta 32(%0)\n"    "   prefetchnta 64(%0)\n"    "   prefetchnta 96(%0)\n"    "   prefetchnta 128(%0)\n"    "   prefetchnta 160(%0)\n"    "   prefetchnta 192(%0)\n"    "   prefetchnta 224(%0)\n"    "   prefetchnta 256(%0)\n"    "   prefetchnta 288(%0)\n"    : : "r" (from) );  if(len >= MIN_LEN)  {    register unsigned long int delta;    /* Align destinition to MMREG_SIZE -boundary */    delta = ((unsigned long int)to)&(MMX_MMREG_SIZE-1);    if(delta)    {      delta=MMX_MMREG_SIZE-delta;      len -= delta;      small_memcpy(to, from, delta);    }    i = len >> 6; /* len/64 */    len&=63;    for(; i>0; i--)    {      __asm__ __volatile__ (      "prefetchnta 320(%0)\n"      "prefetchnta 352(%0)\n"      "movq (%0), %%mm0\n"      "movq 8(%0), %%mm1\n"      "movq 16(%0), %%mm2\n"      "movq 24(%0), %%mm3\n"      "movq 32(%0), %%mm4\n"      "movq 40(%0), %%mm5\n"      "movq 48(%0), %%mm6\n"      "movq 56(%0), %%mm7\n"      "movntq %%mm0, (%1)\n"      "movntq %%mm1, 8(%1)\n"      "movntq %%mm2, 16(%1)\n"      "movntq %%mm3, 24(%1)\n"      "movntq %%mm4, 32(%1)\n"      "movntq %%mm5, 40(%1)\n"      "movntq %%mm6, 48(%1)\n"      "movntq %%mm7, 56(%1)\n"      :: "r" (from), "r" (to) : "memory");      from = ((const unsigned char *)from) + 64;      to = ((unsigned char *)to) + 64;    }     /* since movntq is weakly-ordered, a "sfence"     * is needed to become ordered again. */    __asm__ __volatile__ ("sfence":::"memory");    __asm__ __volatile__ ("emms":::"memory");  }  /*   *	Now do the tail of the block   */  if(len) linux_kernel_memcpy_impl(to, from, len);  return retval;}#endif /* _MSC_VER */#endif /* ARCH_X86 *//* SDL_memcpy is a macro, use IPTV_memcpy where function pointer is required */static __inline__ void* IPTV_memcpy(void * src, const void * dst, size_t len){    SDL_memcpy(src, dst, len);}#endif // MEMCPY_H