?? main.lst
字號(hào):
232 2 if (SPI_SO)
233 2 Data |= 0x01;
234 2 else
235 2 Data &= 0xfe;
236 2
237 2 _nop_();
238 2 _nop_();
239 2 _nop_();
C51 COMPILER V7.20 MAIN 09/04/2008 13:22:12 PAGE 5
240 2 _nop_();
241 2
242 2 SPI_SCK=1;
243 2
244 2 _nop_();
245 2 _nop_();
246 2 }
247 1 return Data;
248 1 }
249 /*
250 uchar _crc_ibutton_update(uchar crc,uchar data_t)
251 {
252 uchar i;
253
254 crc = crc^data_t;
255 for (i = 0; i < 8; i++)
256 {
257 if (crc & 0x01)
258 crc = (crc >> 1)^0x8C;
259 else
260 crc >>= 1;
261 }
262
263 return crc;
264 }
265 // 8位CRC檢驗(yàn)碼
266 uchar crc8_ibutton(uchar *data_t, uchar n)
267 {
268 char crc = 0x00;
269 while(n)
270 {
271 crc = _crc_ibutton_update(crc, *data_t ++);
272 --n;
273 }
274
275 return crc;
276
277 }*/
278 void SPI_Master_Init()
279 {
280 1 //設(shè)置SS SI SCK為輸出(P0.2 P0.5 P0.4)(11開(kāi)漏輸出，10僅為輸入（高阻）,01推挽（上拉）,準(zhǔn)雙向口)，其他為輸入
-P0.3
281 1 P0M1 =0x08;
282 1 P0M2 =0x34;
283 1 P1M1 =0x40; //P1.2 P1.3只能配置為輸入口或開(kāi)漏口。
284 1 P2M2 =0x00;
285 1 }/*
286 void mcu_init()
287 {
288 SPI_Master_Init();
289 }*/
290 void halSpiStrobe(BYTE strobe)
291 {
292 1 OpenSpi();
293 1 WriteByte(strobe);
294 1 SPI_WAIT();
295 1 CloseSpi();//拉高CS，數(shù)據(jù)發(fā)送完畢
296 1 }
297 BYTE halSpiReadReg(BYTE addr)
298 {
299 1 uchar x;
300 1 x=0;
C51 COMPILER V7.20 MAIN 09/04/2008 13:22:12 PAGE 6
301 1 OpenSpi();
302 1 WriteByte(addr|READ_SINGLE);
303 1 SPI_WAIT();
304 1 x=ReadByte();
305 1 CloseSpi();
306 1
307 1 return x;
308 1 }/**/
309
310 void halSpiWriteReg(BYTE addr,BYTE value)
311 {
312 1 OpenSpi();
313 1 WriteByte(addr);
314 1 SPI_WAIT();
315 1 WriteByte(value);
316 1 SPI_WAIT();
317 1 CloseSpi();
318 1 }
319 void halSpiWriteBurstReg(BYTE addr, BYTE *buffer, BYTE count)
320 {
321 1 uchar i;
322 1 OpenSpi();
323 1 WriteByte(addr|WRITE_BURST);
324 1 SPI_WAIT();
325 1 for(i=0;i<count;i++)
326 1 {
327 2 WriteByte(buffer[i]);
328 2 SPI_WAIT();
329 2 }
330 1 CloseSpi();
331 1 }
332 void halSpiReadBurstReg(BYTE addr, BYTE *buffer, BYTE count)
333 {
334 1 uchar i;
335 1 OpenSpi();
336 1 WriteByte(addr|READ_BURST);
337 1 SPI_WAIT();
338 1 for(i=0;i<count;i++)
339 1 {
340 2 buffer[i]=ReadByte();
341 2 SPI_WAIT();
342 2 }
343 1 CloseSpi();
344 1 }/**/
345 BYTE halSpiReadStatus(BYTE addr)
346 {
347 1 uchar x;
348 1 OpenSpi();
349 1 WriteByte(addr|READ_BURST);
350 1 SPI_WAIT();
351 1 x=ReadByte();
352 1 CloseSpi();
353 1
354 1 return x;
355 1 }
356 void RESET_CCxxx0()
357 {
358 1 // OpenSpi();
359 1 SPI_CS=0;
360 1 while(SPI_SO);
361 1 WriteByte(CCxxx0_SRES);
362 1 SPI_WAIT();
C51 COMPILER V7.20 MAIN 09/04/2008 13:22:12 PAGE 7
363 1 while(SPI_SO);
364 1 CloseSpi();
365 1 }
366 void POWER_UP_RESET_CCxxx0()
367 {
368 1 CloseSpi();//1
369 1 halWait(1);
370 1 OpenSpi();//0
371 1 halWait(1);
372 1 CloseSpi();//1
373 1 halWait(41);
374 1 RESET_CCxxx0();
375 1 }
376 BOOL halRfReceivePacket( uchar *rxBuffer, uchar *length)
377 {
378 1 uchar status[2];
379 1 uchar packetLength;
380 1 // halSpiStrobe(CCxxx0_SRX);
381 1 // Wait for GDO0 to be set -> sync received
382 1 // while (!SPI_GDO0);
383 1
384 1 // Wait for GDO0 to be cleared -> end of packet
385 1 // while (SPI_GDO0);
386 1 if (( halSpiReadStatus(CCxxx0_RXBYTES) & BYTES_IN_RXFIFO))//如果接的字節(jié)數(shù)不為0
387 1 {
388 2 // Read length byte
389 2 packetLength = halSpiReadReg(CCxxx0_RXFIFO);//讀出第一個(gè)字節(jié)，此字節(jié)為該幀數(shù)據(jù)長(zhǎng)度
390 2
391 2 // Read data from RX FIFO and store in rxBuffer
392 2 if (packetLength <= *length)//如果所要的有效數(shù)據(jù)長(zhǎng)度小于等于接收到的數(shù)據(jù)包的長(zhǎng)度
393 2 {
394 3 halSpiReadBurstReg(CCxxx0_RXFIFO, rxBuffer, packetLength);
395 3 *length = packetLength;//把接收數(shù)據(jù)長(zhǎng)度的修改為當(dāng)前數(shù)據(jù)的長(zhǎng)度
396 3
397 3 // Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
398 3 halSpiReadBurstReg( CCxxx0_RXFIFO, status, 2); //讀出CRC校驗(yàn)位
399 3
400 3 // MSB of LQI is the CRC_OK bit
401 3 // return (status[LQI] & CRC_OK);//如果校驗(yàn)成功返回接收成功
402 3 return 1;
403 3 }
404 2 else
405 2 {
406 3 *length = packetLength;
407 3
408 3 // Make sure that the radio is in IDLE state before flushing the FIFO
409 3 // (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point)
410 3 halSpiStrobe(CCxxx0_SIDLE);
411 3
412 3 // Flush RX FIFO
413 3 halSpiStrobe(CCxxx0_SFRX);
414 3 return FALSE;
415 3 }
416 2 }
417 1 else
418 1 return FALSE;
419 1 }/**/
420 //-------------------------------------------------------------------------------------------------------
421 // 2.4G
422 // Chipcon
423 // Product = CC2500
424 // Chip version = E (VERSION = 0x03)
C51 COMPILER V7.20 MAIN 09/04/2008 13:22:12 PAGE 8
425 // Crystal accuracy = 10 ppm
426 // X-tal frequency = 26 MHz
427 // RF output power = 0 dBm
428 // RX filterbandwidth = 541.666667 kHz
429 // Phase = 1
430 // Datarate = 249.938965 kBaud
431 // Modulation = (7) MSK
432 // Manchester enable = (0) Manchester disabled
433 // RF Frequency = 2432.999908 MHz
434 // Channel spacing = 199.951172 kHz
435 // Channel number = 0
436 // Optimization = Sensitivity
437 // Sync mode = (3) 30/32 sync word bits detected
438 // Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
439 // CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
440 // Forward Error Correction = (0) FEC disabled
441 // Length configuration = (1) Variable length packets, packet length configured by the first received byte
- after sync word.
442 // Packetlength = 255
443 // Preamble count = (2) 4 bytes
444 // Append status = 1
445 // Address check = (0) No address check
446 // FIFO autoflush = 0
447 // Device address = 0
448 // GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end
- of the packet
449 // GDO2 signal selection = (41) CHIP_RDY
450 void cc2500_init()
451 { uchar xx,dat;
452 1
453 1 POWER_UP_RESET_CCxxx0();
454 1 xx=0x00;
455 1 // xx=halSpiReadStatus(0x30);
456 1
457 1 // 設(shè)置寄存器值
458 1 halSpiWriteReg(CCxxx0_PATABLE, 0xFE);
459 1 dat=halSpiReadReg(CCxxx0_PATABLE);
460 1 halSpiWriteReg(CCxxx0_FSCTRL1,0x07);
461 1 halSpiWriteReg(CCxxx0_FSCTRL0,0x00);
462 1
463 1 halSpiWriteReg(CCxxx0_FREQ2,0x5D);
464 1 halSpiWriteReg(CCxxx0_FREQ1,0x93);
465 1 halSpiWriteReg(CCxxx0_FREQ0,0xB1);
466 1
467 1 halSpiWriteReg(CCxxx0_MDMCFG4,0x2D);
468 1 halSpiWriteReg(CCxxx0_MDMCFG3,0x3B);
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