#include "..\inc\def.h"
//IDE's CS0			->	CPU's A2
//IDE's CS1			->	CPU's A1
//IDE's A2			->	CPU's A3
//IDE's A1			->	CPU's A5
//IDE's A0			->	CPU's A4

/*
==========================================================================
|      | -CS0 | -CS1 | HA2 | HA1 | HA0 |       RD    |      WR     | Offset|
|ADDR.----+-----+-----+----+----+-----------------------------------|
|       |  A2  |   A1   |  A3   |  A5  |  A4  |       Command Block       |       |
|----+----+-----+-----+----+-----+---------------------------+-------|
| 1F0 |   0   |    1   |    0    |   0   |   0   |Data Reg.    |Data Reg.    | 0x100 |
| 1F1 |   0   |    1   |    0    |   0   |   1   |Error Reg.   |Features Reg.| 0x300 |
| 1F2 |   0   |    1   |    0    |   1   |   0   |SEC CNT Reg. |SEC CNT Reg. | 0x900 |
| 1F3 |   0   |    1   |    0    |   1   |   1   |SEC NUM Reg. |SEC NUM Reg. | 0xb00 |
| 1F4 |   0   |    1   |    1    |   0   |   0   |CYL LOW Reg. |CYL LOW Reg. | 0x500 |
| 1F5 |   0   |    1   |    1    |   0   |   1   |CYL HIGH Reg.|CYL HIGH Reg.| 0x700 |
| 1F6 |   0   |    1   |    1    |   1   |   0   |Drv/Head Reg.|Drv/Head Reg.| 0xd00 |
| 1F7 |   0   |    1   |    1    |   1   |   1   |Status Reg.  |Status Reg.  | 0xf00 |
|-------------------------------------------------------------------------|
|       |        |        |          |        |     |       Contorl Block       |       |
|----+----+----+------+----+-----+---------------------------|       |
| 3F6 |   1   |   0    |    1    |  1    |  0  |AltStatus Reg|Dev Ctrl Reg | 0xc80 |
| 3F7 |   1   |   0    |    1    |  1    |  1  |Drv Addr Reg.|    ---      | 0xe80 |
==========================================================================|
*/
// Command Block Registers //
//Little Endiann   IDE=GCS2
#define Data_Reg			(*(volatile U16*)0x04000002)	//	R/W		->1F0h
#define Error_Reg		(*(volatile U8*)0x04000012)	//	R only	->1F1h
#define Features_Reg		(*(volatile U8*)0x04000012)	//	W only	->1F1h
#define Sector_Count		(*(volatile U8*)0x04000022)	//	R/W		->1F2h
#define Sector_Number	(*(volatile U8*)0x04000032)	//	R/W		->1F3h
#define Cylinder_Low		(*(volatile U8*)0x0400000a)	//	R/W		->1F4h
#define Cylinder_High		(*(volatile U8*)0x0400001a)	//	R/W		->1F5h
#define SDH				(*(volatile U8*)0x0400002a)	//	R/W		->1F6h(Driver/Head)
#define Status_Reg		(*(volatile U8*)0x0400003a)	//	R		->1F7h
#define Command_Reg	(*(volatile U8*)0x0400003a)	//	W		->1F7h
// Control Block Registers //
#define Alt_Status_Reg	(*(volatile U8*)0x0400002c)	//	R		->3F6h
#define Dev_control_Reg	(*(volatile U8*)0x0400002c)	//	W		->3F6h
#define Drv_addr_Reg	(*(volatile U8*)0x0400003c)	//	R		->3F7h
/*the following define is used for LBA addressing mode*/
/*        LBA addressing register convert             */
/*
==========================================================
|Reg_Name| D7  | D6  | D5  | D4  | D3  | D2  | D1  | D0  |
|--------+-----+-----+-----+-----+-----+-----+-----+-----|
| LBA_0  | LBA7| LBA6| LBA5| LBA4| LBA3| LBA2| LBA1| LBA0|
==========================================================

==========================================================
|Reg_Name| D7  | D6  | D5  | D4  | D3  | D2  | D1  | D0  |
|--------+-----+-----+-----+-----+-----+-----+-----+-----|
| LBA_1  |LBA15|LBA14|LBA13|LBA12|LBA11|LBA10| LBA9| LBA8|
==========================================================

==========================================================
|Reg_Name| D7  | D6  | D5  | D4  | D3  | D2  | D1  | D0  |
|--------+-----+-----+-----+-----+-----+-----+-----+-----|
| LBA_2  |LBA23|LBA22|LBA21|LBA20|LBA19|LBA18|LBA17|LBA16|
==========================================================

==========================================================
|Reg_Name| D7  | D6  | D5  | D4  | D3  | D2  | D1  | D0  |
|--------+-----+-----+-----+-----+-----+-----+-----+-----|
| LBA_3  |  1  | LBA |  1  | DRV |LBA27|LBA26|LBA25|LBA24|
==========================================================
*/
#define LBA0			Sector_Number
#define LBA1			Cylinder_Low
#define LBA2			Cylinder_High
#define LBA3			SDH



// The Following Master/Slave Define //
#define Master_DRV	0xE0
#define Slave_DRV	0xF0
#define Current_DRV Slave_DRV	//Select Slave Driver






// The Following is ATA Command Define //
#define Check_Power_Mode			0xE5
#define Check_Power_Mode_Alt	    0x98
#define Disable_Password			0xF6
#define Erase_Prepare				0xF3
#define Erase_Unit					0xF4
#define Execute_Drv_Diag			0x90
#define Format_Track				0x50
#define Freeze_Lock					0xF5
#define Identify_Drive				0xEC
		#define Drv_Cylinders_Offset    2
		#define Drv_Heads_Offset		6
		#define Drv_Sectors_Offset		12
		#define Drv_Total_Addr_Sectors_Offset 120	
		#define Drv_NameLong			40
		#define Drv_Name_Offset			54
#define Idle							0xE3
#define Idle_Alt						0x97
#define Idle_Immediate					0xE1
#define Idle_Immediate_Alt				0x95
#define Init_Drv_Parameters				0x91
#define Read_Buffer						0xE4
#define Read_DMA_Retry					0xC8
#define Read_DMA_NoRetry				0xC9
#define Read_Long_Retry					0x22
#define Read_Long_NoRetry				0x23
#define Read_Multiple					0xC4
#define Read_Sectors_Retry				0x20
#define Read_Sectors_NoRetry			0x21
#define Read_Vfy_Sectors_Retry		    0x40
#define Read_Vfy_Sectors_NoRetry	    0x41
#define Recalibrate						0x10
#define Seek							0x70
#define Set_Features					0xEF
#define Set_Multiple					0xC6
#define Set_Password					0xF1
#define Sleep							0xE6
#define Sleep_Alt						0x99
#define Standby							0xE2
#define Standby_Alt						0x96
#define Standby_Immediate				0xE0
#define Standby_Immediate_Alt			0x94
#define Unlock							0xF2
#define Write_Buffer					0xE8
#define Write_DMA_Retry					0xCA
#define Write_DMA_NoRetry				0xCB
#define Write_Long_Retry				0x32
#define Write_Long_NoRetry		    	0x33
#define Write_Multiple					0xC5
#define Write_Sectors_Retry				0x30
#define Write_Sectors_NoRetry			0x31
#define Write_Verify					0x3C
// The Following is Diagnostic Code Define //
#define No_Err_Detected					0x01
#define Formatter_Device_Err			0x02
#define Sector_Buf_Err					0x03
#define ECC_Circuitry_Err				0x04
#define MCU_Err							0x05
#define Slave_DRV_Failed				0x80

////////////////////////////////////////
// The Following is Some Macro Define //
////////////////////////////////////////
#define HDD_Sector_Size		512
#define ATA_OK				0x00
#define ATA_FAIL			0xFF
//Status(Alternate) Register^0=ERR
//Status(Alternate) Register^1=IDX
//Status(Alternate) Register^2=COR
//Status(Alternate) Register^3=DRQ
//Status(Alternate) Register^4=DSC
//Status(Alternate) Register^5=DWF
//Status(Alternate) Register^6=RDY
//Status(Alternate) Register^7=BSY


// The Following is ATA Function Delaear //
U8 Read_Sectors(U8 Drv,U32 LBA,U8 *buf);
U8 Write_Sectors(U8 Drv,U8 Sec_Num,U32 LBA,U8 *buf);
void Set_StandBy_Immediate(U8 DRV);
void Set_Idle_Immediate(U8 DRV);
void Identify_Drv(U8 DRV);
void ATA_Test(void);
////
extern U16 Drv_Cylinders;
extern U16 Drv_Heads;
extern U16 Drv_Sectors;
extern U32 Drv_Total_Addr_Sectors;
extern U8 Drv_Name[Drv_NameLong];