?? 2410addr.inc
字號:
#============================================================================================================================================================================================================================================
# File Name : 2410addr.s
# Author : embest
# Descript : S3C2410 Define Address Register (Assembly)
# History :
# (1) R.X.Huang, Programming start, March 12, 2005
#============================================================================================================================================================================================================================================
.include "option.inc"
#=============================================================================================
# Memory control
#=============================================================================================
.equ BWSCON , 0x48000000 @ Bus width & wait status
.equ BANKCON0 , 0x48000004 @ Boot ROM control
.equ BANKCON1 , 0x48000008 @ BANK1 control
.equ BANKCON2 , 0x4800000c @ BANK2 cControl
.equ BANKCON3 , 0x48000010 @ BANK3 control
.equ BANKCON4 , 0x48000014 @ BANK4 control
.equ BANKCON5 , 0x48000018 @ BANK5 control
.equ BANKCON6 , 0x4800001c @ BANK6 control
.equ BANKCON7 , 0x48000020 @ BANK7 control
.equ REFRESH , 0x48000024 @ DRAM/SDRAM refresh
.equ BANKSIZE , 0x48000028 @ Flexible Bank Size
.equ MRSRB6 , 0x4800002c @ Mode register set for SDRAM
.equ MRSRB7 , 0x48000030 @ Mode register set for SDRAM
#=============================================================================================
# USB Host
#=============================================================================================
#=============================================================================================
# INTERRUPT
#=============================================================================================
.equ SRCPND , 0x4a000000 @ Interrupt request status
.equ INTMOD , 0x4a000004 @ Interrupt mode control
.equ INTMSK , 0x4a000008 @ Interrupt mask control
.equ PRIORITY , 0x4a00000c @ IRQ priority control
.equ INTPND , 0x4a000010 @ Interrupt request status
.equ INTOFFSET , 0x4a000014 @ Interruot request source offset
.equ SUSSRCPND , 0x4a000018 @ Sub source pending
.equ INTSUBMSK , 0x4a00001c @ Interrupt sub mask
#=============================================================================================
# DMA
#=============================================================================================
.equ DISRC0 , 0x4b000000 @ DMA 0 Initial source
.equ DISRCC0 , 0x4b000004 @ DMA 0 Initial source control
.equ DIDST0 , 0x4b000008 @ DMA 0 Initial Destination
.equ DIDSTC0 , 0x4b00000c @ DMA 0 Initial Destination control
.equ DCON0 , 0x4b000010 @ DMA 0 Control
.equ DSTAT0 , 0x4b000014 @ DMA 0 Status
.equ DCSRC0 , 0x4b000018 @ DMA 0 Current source
.equ DCDST0 , 0x4b00001c @ DMA 0 Current destination
.equ DMASKTRIG0, 0x4b000020 @ DMA 0 Mask trigger
.equ DISRC1 , 0x4b000040 @ DMA 1 Initial source
.equ DISRCC1 , 0x4b000044 @ DMA 1 Initial source control
.equ DIDST1 , 0x4b000048 @ DMA 1 Initial Destination
.equ DIDSTC1 , 0x4b00004c @ DMA 1 Initial Destination control
.equ DCON1 , 0x4b000050 @ DMA 1 Control
.equ DSTAT1 , 0x4b000054 @ DMA 1 Status
.equ DCSRC1 , 0x4b000058 @ DMA 1 Current source
.equ DCDST1 , 0x4b00005c @ DMA 1 Current destination
.equ DMASKTRIG1, 0x4b000060 @ DMA 1 Mask trigger
.equ DISRC2 , 0x4b000080 @ DMA 2 Initial source
.equ DISRCC2 , 0x4b000084 @ DMA 2 Initial source control
.equ DIDST2 , 0x4b000088 @ DMA 2 Initial Destination
.equ DIDSTC2 , 0x4b00008c @ DMA 2 Initial Destination control
.equ DCON2 , 0x4b000090 @ DMA 2 Control
.equ DSTAT2 , 0x4b000094 @ DMA 2 Status
.equ DCSRC2 , 0x4b000098 @ DMA 2 Current source
.equ DCDST2 , 0x4b00009c @ DMA 2 Current destination
.equ DMASKTRIG2, 0x4b0000a0 @ DMA 2 Mask trigger
.equ DISRC3 , 0x4b0000c0 @ DMA 3 Initial source
.equ DISRCC3 , 0x4b0000c4 @ DMA 3 Initial source control
.equ DIDST3 , 0x4b0000c8 @ DMA 3 Initial Destination
.equ DIDSTC3 , 0x4b0000cc @ DMA 3 Initial Destination control
.equ DCON3 , 0x4b0000d0 @ DMA 3 Control
.equ DSTAT3 , 0x4b0000d4 @ DMA 3 Status
.equ DCSRC3 , 0x4b0000d8 @ DMA 3 Current source
.equ DCDST3 , 0x4b0000dc @ DMA 3 Current destination
.equ DMASKTRIG3, 0x4b0000e0 @ DMA 3 Mask trigger
#=========================================================================================================================================================================
# CLOCK & POWER MANAGEMENT
#=========================================================================================================================================================================
.equ LOCKTIME , 0x4c000000 @ PLL lock time counter
.equ MPLLCON , 0x4c000004 @ MPLL Control
.equ UPLLCON , 0x4c000008 @ UPLL Control
.equ CLKCON , 0x4c00000c @ Clock generator control
.equ CLKSLOW , 0x4c000010 @ Slow clock control
.equ CLKDIVN , 0x4c000014 @ Clock divider control
#=============================================================================================
# LCD CONTROLLER
#=============================================================================================
.equ LCDCON1 , 0x4d000000 @ LCD control 1
.equ LCDCON2 , 0x4d000004 @ LCD control 2
.equ LCDCON3 , 0x4d000008 @ LCD control 3
.equ LCDCON4 , 0x4d00000c @ LCD control 4
.equ LCDCON5 , 0x4d000010 @ LCD control 5
.equ LCDSADDR1, 0x4d000014 @ STN/TFT Frame buffer start address 1
.equ LCDSADDR2, 0x4d000018 @ STN/TFT Frame buffer start address 2
.equ LCDSADDR3, 0x4d00001c @ STN/TFT Virtual screen address set
.equ REDLUT , 0x4d000020 @ STN Red lookup table
.equ GREENLUT , 0x4d000024 @ STN Green lookup table
.equ BLUELUT , 0x4d000028 @ STN Blue lookup table
.equ DITHMODE , 0x4d00004c @ STN Dithering mode
.equ TPAL , 0x4d000050 @ TFT Temporary palette
.equ LCDINTPND, 0x4d000054 @ LCD Interrupt pending
.equ LCDSRCPND, 0x4d000058 @ LCD Interrupt source
.equ LCDINTMSK, 0x4d00005c @ LCD Interrupt mask
.equ LPCSEL , 0x4d000060 @ LPC3600 Control
#=============================================================================================
# NAND flash
#=============================================================================================
.equ NFCONF , 0x4e000000 @ NAND Flash configuration
.equ NFCMD , 0x4e000004 @ NADD Flash command
.equ NFADDR , 0x4e000008 @ NAND Flash address
.equ NFDATA , 0x4e00000c @ NAND Flash data
.equ NFSTAT , 0x4e000010 @ NAND Flash operation status
.equ NFECC , 0x4e000014 @ NAND Flash ECC
#=============================================================================================
# UART
#=============================================================================================
.equ ULCON0 , 0x50000000 @ UART 0 Line control
.equ UCON0 , 0x50000004 @ UART 0 Control
.equ UFCON0 , 0x50000008 @ UART 0 FIFO control
.equ UMCON0 , 0x5000000c @ UART 0 Modem control
.equ UTRSTAT0 , 0x50000010 @ UART 0 Tx/Rx status
.equ UERSTAT0 , 0x50000014 @ UART 0 Rx error status
.equ UFSTAT0 , 0x50000018 @ UART 0 FIFO status
.equ UMSTAT0 , 0x5000001c @ UART 0 Modem status
.equ UBRDIV0 , 0x50000028 @ UART 0 Baud rate divisor
.equ ULCON1 , 0x50004000 @ UART 1 Line control
.equ UCON1 , 0x50004004 @ UART 1 Control
.equ UFCON1 , 0x50004008 @ UART 1 FIFO control
.equ UMCON1 , 0x5000400c @ UART 1 Modem control
.equ UTRSTAT1 , 0x50004010 @ UART 1 Tx/Rx status
.equ UERSTAT1 , 0x50004014 @ UART 1 Rx error status
.equ UFSTAT1 , 0x50004018 @ UART 1 FIFO status
.equ UMSTAT1 , 0x5000401c @ UART 1 Modem status
.equ UBRDIV1 , 0x50004028 @ UART 1 Baud rate divisor
.equ ULCON2 , 0x50008000 @ UART 2 Line control
.equ UCON2 , 0x50008004 @ UART 2 Control
.equ UFCON2 , 0x50008008 @ UART 2 FIFO control
.equ UMCON2 , 0x5000800c @ UART 2 Modem control
.equ UTRSTAT2 , 0x50008010 @ UART 2 Tx/Rx status
.equ UERSTAT2 , 0x50008014 @ UART 2 Rx error status
.equ UFSTAT2 , 0x50008018 @ UART 2 FIFO status
.equ UMSTAT2 , 0x5000801c @ UART 2 Modem status
.equ UBRDIV2 , 0x50008028 @ UART 2 Baud rate divisor
.IFDEF BIG_ENDIAN__
.equ UTXH0 , 0x50000023 @ UART 0 Transmission Hold
.equ URXH0 , 0x50000027 @ UART 0 Receive buffer
.equ UTXH1 , 0x50004023 @ UART 1 Transmission Hold
.equ URXH1 , 0x50004027 @ UART 1 Receive buffer
.equ UTXH2 , 0x50008023 @ UART 2 Transmission Hold
.equ URXH2 , 0x50008027 @ UART 2 Receive buffer
.ELSEIF @ Little Endian
UTXH0 , 0x50000020 @ UART 0 Transmission Hold
URXH0 , 0x50000024 @ UART 0 Receive buffer
UTXH1 , 0x50004020 @ UART 1 Transmission Hold
URXH1 , 0x50004024 @ UART 1 Receive buffer
UTXH2 , 0x50008020 @ UART 2 Transmission Hold
URXH2 , 0x50008024 @ UART 2 Receive buffer
.ENDIF
#=============================================================================================
# PWM TIMER
#=============================================================================================
.equ TCFG0 , 0x51000000 @ Timer 0 configuration
.equ TCFG1 , 0x51000004 @ Timer 1 configuration
.equ TCON , 0x51000008 @ Timer control
.equ TCNTB0, 0x5100000c @ Timer count buffer 0
.equ TCMPB0, 0x51000010 @ Timer compare buffer 0
.equ TCNTO0, 0x51000014 @ Timer count observation 0
.equ TCNTB1, 0x51000018 @ Timer count buffer 1
.equ TCMPB1, 0x5100001c @ Timer compare buffer 1
.equ TCNTO1, 0x51000020 @ Timer count observation 1
.equ TCNTB2, 0x51000024 @ Timer count buffer 2
.equ TCMPB2, 0x51000028 @ Timer compare buffer 2
.equ TCNTO2, 0x5100002c @ Timer count observation 2
.equ TCNTB3, 0x51000030 @ Timer count buffer 3
.equ TCMPB3, 0x51000034 @ Timer compare buffer 3
.equ TCNTO3, 0x51000038 @ Timer count observation 3
.equ TCNTB4, 0x5100003c @ Timer count buffer 4
.equ TCNTO4, 0x51000040 @ Timer count observation 4
#=============================================================================================
# USB DEVICE
#=============================================================================================
.IFDEF BIG_ENDIAN__
.equ FUNC_ADDR_REG , 0x52000143 @ Function address
.equ PWR_REG , 0x52000147 @ Power management
.equ EP_INT_REG , 0x5200014b @ EP Interrupt pending and clear
.equ USB_INT_REG , 0x5200015b @ USB Interrupt pending and clear
.equ EP_INT_EN_REG , 0x5200015f @ Interrupt enable
.equ USB_INT_EN_REG , 0x5200016f
.equ FRAME_NUM1_REG , 0x52000173 @ Frame number lower byte
.equ FRAME_NUM2_REG , 0x52000177 @ Frame number lower byte
.equ INDEX_REG , 0x5200017b @ Register index
.equ MAXP_REG , 0x52000183 @ Endpoint max packet
.equ EP0_CSR , 0x52000187 @ Endpoint 0 status
.equ IN_CSR1_REG , 0x52000187 @ In endpoint control status
.equ IN_CSR2_REG , 0x5200018b
.equ OUT_CSR1_REG , 0x52000193 @ Out endpoint control status
.equ OUT_CSR2_REG , 0x52000197
.equ OUT_FIFO_CNT1_REG, 0x5200019b @ Endpoint out write count
.equ OUT_FIFO_CNT2_REG, 0x5200019f
.equ EP0_FIFO , 0x520001c3 @ Endpoint 0 FIFO
.equ EP1_FIFO , 0x520001c7 @ Endpoint 1 FIFO
.equ EP2_FIFO , 0x520001cb @ Endpoint 2 FIFO
.equ EP3_FIFO , 0x520001cf @ Endpoint 3 FIFO
.equ EP4_FIFO , 0x520001d3 @ Endpoint 4 FIFO
.equ EP1_DMA_CON , 0x52000203 @ EP1 DMA interface control
.equ EP1_DMA_UNIT , 0x52000207 @ EP1 DMA Tx unit counter
.equ EP1_DMA_FIFO , 0x5200020b @ EP1 DMA Tx FIFO counter
.equ EP1_DMA_TTC_L , 0x5200020f @ EP1 DMA total Tx counter
.equ EP1_DMA_TTC_M , 0x52000213
.equ EP1_DMA_TTC_H , 0x52000217
.equ EP2_DMA_CON , 0x5200021b @ EP2 DMA interface control
.equ EP2_DMA_UNIT , 0x5200021f @ EP2 DMA Tx unit counter
.equ EP2_DMA_FIFO , 0x52000223 @ EP2 DMA Tx FIFO counter
.equ EP2_DMA_TTC_L , 0x52000227 @ EP2 DMA total Tx counter
.equ EP2_DMA_TTC_M , 0x5200022b
.equ EP2_DMA_TTC_H , 0x5200022f
.equ EP3_DMA_CON , 0x52000243 @ EP3 DMA interface control
.equ EP3_DMA_UNIT , 0x52000247 @ EP3 DMA Tx unit counter
.equ EP3_DMA_FIFO , 0x5200024b @ EP3 DMA Tx FIFO counter
.equ EP3_DMA_TTC_L , 0x5200024f @ EP3 DMA total Tx counter
.equ EP3_DMA_TTC_M , 0x52000253
.equ EP3_DMA_TTC_H , 0x52000257
.equ EP4_DMA_CON , 0x5200025b @ EP4 DMA interface control
.equ EP4_DMA_UNIT , 0x5200025f @ EP4 DMA Tx unit counter
.equ EP4_DMA_FIFO , 0x52000263 @ EP4 DMA Tx FIFO counter
.equ EP4_DMA_TTC_L , 0x52000267 @ EP4 DMA total Tx counter
.equ EP4_DMA_TTC_M , 0x5200026b
.equ EP4_DMA_TTC_H , 0x5200026f
.ELSEIF @Little Endian
.equ FUNC_ADDR_REG , 0x52000140 @ Function address
.equ PWR_REG , 0x52000144 @ Power management
.equ EP_INT_REG , 0x52000148 @ EP Interrupt pending and clear
.equ USB_INT_REG , 0x52000158 @ USB Interrupt pending and clear
.equ EP_INT_EN_REG , 0x5200015c @ Interrupt enable
.equ USB_INT_EN_REG , 0x5200016c
.equ FRAME_NUM1_REG , 0x52000170 @ Frame number lower byte
.equ FRAME_NUM2_REG , 0x52000174 @ Frame number lower byte
.equ INDEX_REG , 0x52000178 @ Register index
.equ MAXP_REG , 0x52000180 @ Endpoint max packet
.equ EP0_CSR , 0x52000184 @ Endpoint 0 status
.equ IN_CSR1_REG , 0x52000184 @ In endpoint control status
.equ IN_CSR2_REG , 0x52000188
.equ OUT_CSR1_REG , 0x52000190 @ Out endpoint control status
.equ OUT_CSR2_REG , 0x52000194
.equ OUT_FIFO_CNT1_REG, 0x52000198 @ Endpoint out write count
.equ OUT_FIFO_CNT2_REG, 0x5200019c
.equ EP0_FIFO , 0x520001c0 @ Endpoint 0 FIFO
.equ EP1_FIFO , 0x520001c4 @ Endpoint 1 FIFO
.equ EP2_FIFO , 0x520001c8 @ Endpoint 2 FIFO
.equ EP3_FIFO , 0x520001cc @ Endpoint 3 FIFO
.equ EP4_FIFO , 0x520001d0 @ Endpoint 4 FIFO
.equ EP1_DMA_CON , 0x52000200 @ EP1 DMA interface control
.equ EP1_DMA_UNIT , 0x52000204 @ EP1 DMA Tx unit counter
.equ EP1_DMA_FIFO , 0x52000208 @ EP1 DMA Tx FIFO counter
.equ EP1_DMA_TTC_L , 0x5200020c @ EP1 DMA total Tx counter
.equ EP1_DMA_TTC_M , 0x52000210
.equ EP1_DMA_TTC_H , 0x52000214
.equ EP2_DMA_CON , 0x52000218 @ EP2 DMA interface control
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