/************************************************************************************/
/* File name:     240x.h                                                            */
/* Last modified: 2002.8.27                                                         */
/* Description:   240x register definitions, Bit codes for BIT instruction       	*/
/* Copy Right:    Zhang Xuejie                                                      */
/************************************************************************************/


/********************************240x CPU core registers*****************************/
#define    IMR          (volatile unsigned int *)0x0004  /* Interrupt Mask Register */
#define	   IFR          (volatile unsigned int *)0x0006  /* Interrupt Flag register */

/**********************System configuration and interrupt registers******************/
#define    SCSR1        (volatile unsigned int *)0x7018    /* System Control & Status register. 1*/
#define	   SCSR2        (volatile unsigned int *)0x7019    /* System Control & Status register. 2*/
#define	   DINR         (volatile unsigned int *)0x701C    /* Device Identification Number register*/
#define	   PIVR         (volatile unsigned int *)0x701E    /* Peripheral Interrupt Vector register*/
#define	   PIRQR0       (volatile unsigned int *)0x7010    /* Peripheral Interrupt Request register 0*/
#define	   PIRQR1       (volatile unsigned int *)0x7011    /* Peripheral Interrupt Request register 1*/
#define	   PIRQR2       (volatile unsigned int *)0x7012    /* Peripheral Interrupt Request register 2*/
#define	   PIACKR0      (volatile unsigned int *)0x7014    /* Peripheral Interrupt Acknowledge register 0*/
#define	   PIACKR1      (volatile unsigned int *)0x7015    /* Peripheral Interrupt Acknowledge register 1*/
#define	   PIACKR2      (volatile unsigned int *)0x7016    /* Peripheral Interrupt Acknowledge register 2*/

/**********************External interrupt configuration registers********************/
#define    XINT1CR      (volatile unsigned int *)0x7070    /* External interrupt 1 control register*/
#define    XINT2CR      (volatile unsigned int *)0x7071    /* External interrupt 2 control register*/

/********************************Digital I/O registers*******************************/
#define    MCRA         (volatile unsigned int *)0x7090    /* I/O Mux Control Register A*/
#define    MCRB         (volatile unsigned int *)0x7092    /* I/O Mux Control Register B*/
#define    MCRC         (volatile unsigned int *)0x7094    /* I/O Mux Control Register C*/
#define    PADATDIR     (volatile unsigned int *)0x7098    /* I/O port A Data & Direction register*/
#define    PBDATDIR     (volatile unsigned int *)0x709A    /* I/O port B Data & Direction register*/
#define    PCDATDIR     (volatile unsigned int *)0x709C    /* I/O port C Data & Direction register*/
#define    PDDATDIR     (volatile unsigned int *)0x709E    /* I/O port D Data & Direction register*/
#define    PEDATDIR     (volatile unsigned int *)0x7095    /* I/O port E Data & Direction register*/
#define    PFDATDIR     (volatile unsigned int *)0x7096    /* I/O port F Data & Direction register*/

/********************************Watchdog (WD) registers*****************************/
#define    WDCNTR       (volatile unsigned int *)0x7023    	 /* WD Counter register */
#define    WDKEY        (volatile unsigned int *)0x7025    	     /* WD Key register */
#define    WDCR         (volatile unsigned int *)0x7029      /* WD Control register */

/*************************************ADC registers**********************************/
#define    ADCTRL1      (volatile unsigned int *)0x70A0    /* ADC Control register 1*/
#define    ADCTRL2      (volatile unsigned int *)0x70A1    /* ADC Control register 2*/
#define    MAX_CONV     (volatile unsigned int *)0x70A2    /* Maximum conversion channels register*/
#define    CHSELSEQ1    (volatile unsigned int *)0x70A3    /* Channel select Sequencing control register 1*/
#define    CHSELSEQ2    (volatile unsigned int *)0x70A4    /* Channel select Sequencing control register 2*/
#define    CHSELSEQ3    (volatile unsigned int *)0x70A5    /* Channel select Sequencing control register 3*/
#define    CHSELSEQ4    (volatile unsigned int *)0x70A6    /* Channel select Sequencing control register 4*/
#define    AUTO_SEQ_SR  (volatile unsigned int *)0x70A7    /* Auto–sequence status register*/
#define    RESULT0      (volatile unsigned int *)0x70A8    /* Conversion result buffer register 0*/
#define    RESULT1      (volatile unsigned int *)0x70A9    /* Conversion result buffer register 1*/
#define    RESULT2      (volatile unsigned int *)0x70Aa    /* Conversion result buffer register 2*/
#define    RESULT3      (volatile unsigned int *)0x70Ab    /* Conversion result buffer register 3*/
#define    RESULT4      (volatile unsigned int *)0x70Ac    /* Conversion result buffer register 4*/
#define    RESULT5      (volatile unsigned int *)0x70Ad    /* Conversion result buffer register 5*/
#define    RESULT6      (volatile unsigned int *)0x70Ae    /* Conversion result buffer register 6*/
#define    RESULT7      (volatile unsigned int *)0x70Af    /* Conversion result buffer register 7*/
#define    RESULT8      (volatile unsigned int *)0x70B0    /* Conversion result buffer register 8*/
#define    RESULT9      (volatile unsigned int *)0x70B1    /* Conversion result buffer register 9*/
#define    RESULT10     (volatile unsigned int *)0x70B2    /* Conversion result buffer register 10*/
#define    RESULT11     (volatile unsigned int *)0x70B3    /* Conversion result buffer register 11*/
#define    RESULT12     (volatile unsigned int *)0x70B4    /* Conversion result buffer register 12*/
#define    RESULT13     (volatile unsigned int *)0x70B5    /* Conversion result buffer register 13*/
#define    RESULT14     (volatile unsigned int *)0x70B6    /* Conversion result buffer register 14*/
#define    RESULT15     (volatile unsigned int *)0x70B7    /* Conversion result buffer register 15*/
#define    CALIBRATION  (volatile unsigned int *)0x70B8    /* Calib result, used to correct subsequent conversions*/
					
/*************************************SPI registers**********************************/
#define    SPICCR       (volatile unsigned int *)0x7040    /* SPI Config Control register*/
#define    SPICTL       (volatile unsigned int *)0x7041    /* SPI Operation Control register*/
#define    SPISTS       (volatile unsigned int *)0x7042    /* SPI Status register */
#define    SPIBRR       (volatile unsigned int *)0x7044    /* SPI Baud rate control register*/
#define    SPIRXEMU     (volatile unsigned int *)0x7046    /* SPI Emulation buffer register*/
#define    SPIRXBUF     (volatile unsigned int *)0x7047    /* SPI Serial receive buffer register*/
#define    SPITXBUF     (volatile unsigned int *)0x7048    /* SPI Serial transmit buffer register*/
#define    SPIDAT       (volatile unsigned int *)0x7049    /* SPI Serial data register*/
#define    SPIPRI       (volatile unsigned int *)0x704F    /* SPI Priority control register*/

/*************************************SCI registers**********************************/
#define    SCICCR       (volatile unsigned int *)0x7050    /* SCI Communication control register*/
#define    SCICTL1      (volatile unsigned int *)0x7051    /* SCI Control register 1 */
#define    SCIHBAUD     (volatile unsigned int *)0x7052    /* SCI Baud Rate MS byte register*/
#define    SCILBAUD     (volatile unsigned int *)0x7053    /* SCI Baud Rate LS byte register*/
#define    SCICTL2      (volatile unsigned int *)0x7054    /* SCI Control register 2 */
#define    SCIRXST      (volatile unsigned int *)0x7055    /* SCI Receiver Status register*/
#define    SCIRXEMU     (volatile unsigned int *)0x7056    /* SCI Emulation Data Buffer register*/
#define    SCIRXBUF     (volatile unsigned int *)0x7057    /* SCI Receiver Data buffer register*/
#define    SCITXBUF     (volatile unsigned int *)0x7059    /* SCI Transmit Data buffer register*/
#define    SCIPRI       (volatile unsigned int *)0x705F    /* SCI Priority control register*/

/****************************Event Manager A (EVA) registers*************************/
#define    GPTCONA      (volatile unsigned int *)0x7400    /* GP Timer control register A*/
#define    T1CNT        (volatile unsigned int *)0x7401    /* GP Timer 1 counter register*/
#define    T1CMPR       (volatile unsigned int *)0x7402    /* GP Timer 1 compare register*/
#define    T1PR         (volatile unsigned int *)0x7403    /* GP Timer 1 period register*/
#define    T1CON        (volatile unsigned int *)0x7404    /* GP Timer 1 control register*/
#define    T2CNT        (volatile unsigned int *)0x7405    /* GP Timer 2 counter register*/
#define    T2CMPR       (volatile unsigned int *)0x7406    /* GP Timer 2 compare register*/
#define    T2PR         (volatile unsigned int *)0x7407    /* GP Timer 2 period register*/
#define    T2CON        (volatile unsigned int *)0x7408    /* GP Timer 2 control register*/
#define    COMCONA      (volatile unsigned int *)0x7411    /* Compare control register A*/
#define    ACTRA        (volatile unsigned int *)0x7413    /* Full compare Action control register A*/
#define    DBTCONA      (volatile unsigned int *)0x7415    /* Dead–band timer control register A*/
#define    CMPR1        (volatile unsigned int *)0x7417    /* Full compare unit compare register1*/
#define    CMPR2        (volatile unsigned int *)0x7418    /* Full compare unit compare register2*/
#define    CMPR3        (volatile unsigned int *)0x7419    /* Full compare unit compare register3*/
#define    CAPCONA      (volatile unsigned int *)0x7420    /* Capture control register A*/
#define    CAPFIFOA     (volatile unsigned int *)0x7422    /* Capture FIFO status register A*/
#define    CAP1FIFO     (volatile unsigned int *)0x7423    /* Capture Channel 1 FIFO Top*/
#define    CAP2FIFO     (volatile unsigned int *)0x7424    /* Capture Channel 2 FIFO Top*/
#define    CAP3FIFO     (volatile unsigned int *)0x7425    /* Capture Channel 3 FIFO Top*/
#define    CAP1FBOT     (volatile unsigned int *)0x7427    /* Bottom reg. of capture FIFO stack 1*/
#define    CAP2FBOT     (volatile unsigned int *)0x7428    /* Bottom reg. of capture FIFO stack 2*/
#define    CAP3FBOT     (volatile unsigned int *)0x7429    /* Bottom reg. of capture FIFO stack 3*/
#define    EVAIMRA      (volatile unsigned int *)0x742C    /* Group A Interrupt Mask Register*/
#define    EVAIMRB      (volatile unsigned int *)0x742D    /* Group B Interrupt Mask Register*/