<?xml version="1.0" encoding="UTF-8"?>
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<messages>
<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">XLXI_3/XLXI_1/CEO</arg> has no load.
</msg>

<msg type="warning" file="LIT" num="395" delta="unknown" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">130</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="4">XLXI_3/XLXI_1/N0,
XLXI_3/XLXI_1/I_Q3/N0,
XLXI_3/XLXI_1/I_Q3/N1,
XLXI_3/XLXI_1/I_Q2/N0,
XLXI_3/XLXI_1/I_Q2/N1</arg>
To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
</msg>

<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>

<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
</msg>

<msg type="warning" file="LIT" num="175" delta="unknown" >Clock buffer is designated to drive clock loads. <arg fmt="%s" index="1">BUFG symbol &quot;clk_40_BUFGP/BUFG&quot; (output signal=clk_40_BUFGP)</arg> has a mix of clock and non-clock loads. Some of the non-clock loads are (maximum of 5 listed):
<arg fmt="%s" index="2">Pin I1 of XLXI_3/XLXI_232
Pin PRE of XLXI_2/BU2/U0/gen_as.fgas/normgen.inblk/rd_rst_int_0
Pin PRE of XLXI_2/BU2/U0/gen_as.fgas/normgen.inblk/wr_rst_reg
Pin PRE of XLXI_2/BU2/U0/gen_as.fgas/normgen.inblk/wr_rst_fb
Pin PRE of XLXI_2/BU2/U0/gen_as.fgas/normgen.inblk/rd_rst_reg</arg>
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">vref_OBUF</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

</messages>