?? xst.xmsgs
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/sjall.vhf</arg>" line <arg fmt="%d" index="2">91</arg>: Unconnected output port '<arg fmt="%s" index="3">full</arg>' of component '<arg fmt="%s" index="4">FIFO</arg>'.
</msg>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/sjall.vhf</arg>" line <arg fmt="%d" index="2">91</arg>: Unconnected output port '<arg fmt="%s" index="3">empty</arg>' of component '<arg fmt="%s" index="4">FIFO</arg>'.
</msg>
<msg type="warning" file="Xst" num="2211" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/sjall.vhf</arg>" line <arg fmt="%d" index="2">91</arg>: Instantiating black box module <<arg fmt="%s" index="3">FIFO</arg>>.
</msg>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/SX.vhf</arg>" line <arg fmt="%d" index="2">740</arg>: Unconnected output port '<arg fmt="%s" index="3">CEO</arg>' of component '<arg fmt="%s" index="4">CB4CE_MXILINX_SX</arg>'.
</msg>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/SX.vhf</arg>" line <arg fmt="%d" index="2">740</arg>: Unconnected output port '<arg fmt="%s" index="3">Q2</arg>' of component '<arg fmt="%s" index="4">CB4CE_MXILINX_SX</arg>'.
</msg>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/SX.vhf</arg>" line <arg fmt="%d" index="2">740</arg>: Unconnected output port '<arg fmt="%s" index="3">Q3</arg>' of component '<arg fmt="%s" index="4">CB4CE_MXILINX_SX</arg>'.
</msg>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/SX.vhf</arg>" line <arg fmt="%d" index="2">740</arg>: Unconnected output port '<arg fmt="%s" index="3">TC</arg>' of component '<arg fmt="%s" index="4">CB4CE_MXILINX_SX</arg>'.
</msg>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/SX.vhf</arg>" line <arg fmt="%d" index="2">759</arg>: Unconnected output port '<arg fmt="%s" index="3">CEO</arg>' of component '<arg fmt="%s" index="4">CB4CE_MXILINX_SX</arg>'.
</msg>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/SX.vhf</arg>" line <arg fmt="%d" index="2">778</arg>: Unconnected output port '<arg fmt="%s" index="3">CEO</arg>' of component '<arg fmt="%s" index="4">CB4CE_MXILINX_SX</arg>'.
</msg>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/SX.vhf</arg>" line <arg fmt="%d" index="2">789</arg>: Unconnected output port '<arg fmt="%s" index="3">CEO</arg>' of component '<arg fmt="%s" index="4">CB4CE_MXILINX_SX</arg>'.
</msg>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/SX.vhf</arg>" line <arg fmt="%d" index="2">800</arg>: Unconnected output port '<arg fmt="%s" index="3">CEO</arg>' of component '<arg fmt="%s" index="4">CB4CE_MXILINX_SX</arg>'.
</msg>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/SX.vhf</arg>" line <arg fmt="%d" index="2">800</arg>: Unconnected output port '<arg fmt="%s" index="3">Q2</arg>' of component '<arg fmt="%s" index="4">CB4CE_MXILINX_SX</arg>'.
</msg>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/SX.vhf</arg>" line <arg fmt="%d" index="2">800</arg>: Unconnected output port '<arg fmt="%s" index="3">Q3</arg>' of component '<arg fmt="%s" index="4">CB4CE_MXILINX_SX</arg>'.
</msg>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/SX.vhf</arg>" line <arg fmt="%d" index="2">800</arg>: Unconnected output port '<arg fmt="%s" index="3">TC</arg>' of component '<arg fmt="%s" index="4">CB4CE_MXILINX_SX</arg>'.
</msg>
<msg type="warning" file="Xst" num="753" delta="unknown" >"<arg fmt="%s" index="1">E:/Application/SJ/FPGA/SX.vhf</arg>" line <arg fmt="%d" index="2">960</arg>: Unconnected output port '<arg fmt="%s" index="3">CEO</arg>' of component '<arg fmt="%s" index="4">CB4CE_MXILINX_SX</arg>'.
</msg>
<msg type="warning" file="Xst" num="653" delta="unknown" >Signal <<arg fmt="%s" index="1">dummy</arg>> is used but never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="unknown" >Signal <<arg fmt="%s" index="1">dummy</arg>> is used but never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
</msg>
<msg type="info" file="Xst" num="2169" delta="unknown" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>
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